Energy-Efficient Computing

Energy-efficient computing encompasses a spectrum of strategies to minimise power consumption and thermal dissipation across software, hardware and system levels without undermining performance or accuracy. Algorithmic approaches exploit the inherent error resilience of many modern workloads—ranging from multimedia processing to machine-learning inference—by adopting techniques such as precision reduction, operand trimming and sparsity-aware pruning. Hardware innovations include specialised low-power arithmetic units, dynamically reconfigurable circuits and in-memory or near-sensor computing platforms that reduce data movement and exploit parallelism. Co-design of hardware and software further amplifies efficiency gains by aligning dataflows, memory hierarchies and control logic with algorithmic requirements. Together, these advances support deployment on battery-powered edge devices, real-time sensor nodes and large-scale data centres, offering extended operational lifetimes, reduced cooling overheads and smaller carbon footprints. Practical applications span Internet-of-Things sensing, on-device neural network training, high-throughput inference accelerators and compact hardware for autonomous systems. As energy costs and environmental impact become ever more critical, interdisciplinary research continues to push the boundaries of sustainable and high-performance computing.

Research from Nature Portfolio

Recent work has demonstrated that combining Booth encoding with Vedic multiplication can yield compact arithmetic units that deliver high throughput while dramatically reducing silicon area and dynamic power. Implemented on both field-programmable and standard-cell platforms, these hybrid multiplier architectures achieve substantial gains in area-delay product for moderate bit-widths, making them attractive for signal-processing and machine-learning kernels. A complementary study introduced a novel hybrid compressor-based binary multiplier tailored for FPGA fabrics, showing significant speed-ups over conventional array and Wallace-tree designs with minimal impact on resource utilisation. Meanwhile, the field of on-device neural-network training has seen the adoption of custom low-bit floating-point representations that constrain parameter exponents and leverage exponent offsets, enabling eight-bit training of benchmark convolutional models with negligible loss in accuracy. This approach holds promise for adaptive, energy-aware learning directly on resource-limited platforms.

Research from all publishers

Outside of the Nature portfolio, two-stage operand trimming in logarithmic multipliers has been developed to remove least-significant bits in successive approximation stages, cutting energy per operation and area in 45 nm technology with only minor quality loss in image and inference pipelines. A reconfigurable design-automation framework now generates approximate circuits with multiple accuracy modes at runtime, enabling dynamic switching between low-power and full-precision operation under user-defined error budgets. In advanced FinFET libraries, such frameworks achieve energy savings exceeding 40 per cent for tight error bounds and can revert gracefully to exact computation when required. Additionally, recursive multiplier topologies built from low-power approximate building blocks exploit controlled carry manipulation to scale from 4×4 to 8×8 designs, reporting up to 45 per cent power reduction and over 80 per cent accuracy retention in convolutional neural-network layers.

Energy-Efficient Computing publication trend

The graph below shows the total number of articles in energy-efficient computing across all publications each year (not limited to Nature Index journals).

Technical terms

Approximate computing: A paradigm that permits bounded inaccuracies in computation to reduce power and area.
Operand trimming: The removal of least-significant bits from inputs to simplify arithmetic and save energy.
Quantisation: The process of mapping continuous or high-precision values to a finite set of levels for efficient hardware implementation.
Hardware accelerator: A specialised processing unit (ASIC, FPGA or NPU) optimised for specific operations to improve energy efficiency.
Reconfigurable accuracy: The ability of a circuit to switch between different approximation levels at runtime based on quality or power requirements.
In-memory computing: An architecture that performs computation within memory arrays to minimise data transfer and energy overhead.
Bit-width reduction: The deliberate reduction of operand or weight precision to lower computation and storage costs.

References

1. A Two-Stage Operand Trimming Approximate Logarithmic Multiplier. IEEE Transactions on Circuits and Systems I Regular Papers (2021).
2. Approximate Recursive Multipliers Using Low Power Building Blocks. IEEE Transactions on Emerging Topics in Computing (2022).
3. Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy. IEEE Access (2020).
4. A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications. Scientific Reports (2023).
5. Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation. Scientific Reports (2024).
6. Resource constrained neural network training. Scientific Reports (2024).