CMOS Voltage Reference Circuit Techniques

CMOS voltage reference circuits form the cornerstone of stable power management in integrated systems, providing a fixed voltage irrespective of supply, temperature and process variations. Traditional bandgap references combine complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages to achieve near-zero temperature coefficients, but often consume significant power and occupy sizeable silicon area. To overcome these limitations, contemporary designs have explored subthreshold operation of MOSFETs, exploiting the exponential I–V relationship at gate biases below the threshold to achieve nano- to pico-watt power consumption. Techniques such as curvature compensation and DIBL (drain-induced barrier lowering) correction have been introduced to refine temperature performance over wide ranges. Process-corner adaptation via replica-selection architectures further enhances accuracy across manufacturing spreads, while resistorless and low-component-count topologies reduce layout overhead. Advances in noise reduction—particularly minimising 1/f noise through removal of noisy error amplifiers or the introduction of chopping—improve stability in precision applications such as MEMS gyroscopes. The convergence of these methods yields references capable of operation at sub-1 V supply levels, with line sensitivities below 0.1 %/V, temperature coefficients in the tens of ppm/°C and power consumption down to picowatts, meeting the stringent demands of energy-harvesting, biomedical and IoT systems.

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Research from all publishers

Recent developments highlight three key innovations. First, an ultralow-noise bandgap reference eliminates the traditional error amplifier and uses an optimised topology to reduce 1/f noise, achieving an integrated output noise of 0.82 μV (0.1–10 Hz) in a 180 nm CMOS process; this directly enhances bias stability in MEMS gyroscope readout circuits. Second, a corner-aware replica-selection design employs multiple NMOS-only replicas optimised for different process corners and selects or merges them at boot time, enabling 1.4 mV absolute accuracy across corners, supply down to 0.2 V and power consumption of 3.9 pW. This method circumvents trimming and non-volatile memory, simplifying low-cost energy-harvesting applications. Third, a two-transistor subthreshold reference with DIBL compensation uses a bias current source to counteract short-channel effects, yielding 307.8 mV reference voltage with line sensitivity as low as 0.020 %/V, a temperature coefficient of 24.8 ppm/°C and power draw of only 21.4 pW. Together, these works exemplify the trend towards ultra-low-power, high-accuracy CMOS references tailored for emerging autonomous and implantable systems.

CMOS Voltage Reference Circuit Techniques publication trend

The graph below shows the total number of articles in cmos voltage reference circuit techniques across all publications each year (not limited to Nature Index journals).

Technical terms

Bandgap reference: A circuit that generates a temperature-independent voltage by summing CTAT and PTAT voltages, typically around 1.2 V.

Subthreshold operation: The regime where MOSFET gate voltage is below threshold, producing an exponential drain current for ultra-low-power biasing.

DIBL (Drain-Induced Barrier Lowering): A short-channel effect where increased drain voltage lowers the source–drain potential barrier, affecting current and temperature behaviour.

PTAT/CTAT: Voltages that respectively increase or decrease in proportion to absolute temperature, used in tandem for temperature compensation.

PSRR (Power Supply Rejection Ratio): A measure of a circuit’s ability to suppress variations in supply voltage from its output reference.

Line sensitivity: The change in reference output per unit change in supply voltage, commonly expressed as %/V.

References

1. A 0.82 μVrms ultralow 1/f noise bandgap reference for a MEMS gyroscope. Microsystems & Nanoengineering (2023).
2. Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. IEEE Access (2023).
3. A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation. Sensors (2023).