Dielectric Engineering in Two-Dimensional Electronics

Dielectric engineering in two-dimensional (2D) electronics centres on the design and integration of insulating materials to control electric fields, enhance carrier mobility and reduce leakage currents in atomically thin transistors and circuits. In contrast to silicon technology, 2D semiconductors present dangling-bond-free surfaces that challenge conventional dielectric deposition, often resulting in ill-defined interfaces and high trap densities. Recent advances have addressed these obstacles through the development of atomically thin crystalline oxides, van der Waals assembly of high-κ films and novel surface treatment methods. Such innovations have yielded ultra-low equivalent oxide thicknesses, steep subthreshold swings and high on/off ratios, paving the way for energy-efficient, ultrascaled devices. By tailoring interface chemistry and dielectric permittivity, researchers aim to unlock the theoretical performance limits of 2D field-effect transistors (FETs) and enable next-generation logic, memory and low-power electronics.

Research from Nature Portfolio

Recent studies have demonstrated the fabrication of a single-crystalline aluminium oxide film only 1.25 nm thick as a top-gate dielectric, formed via intercalative oxidation at room temperature. The resulting transistors exhibit a subthreshold swing approaching the thermal limit, an on/off current ratio of 10^8 and minimal hysteresis, confirming compatibility with negative-capacitance and spin-based devices. Another strategy employs a dry transfer of wafer-scale, sub-3 nm high-κ dielectrics pre-deposited by atomic layer deposition onto MoS2 monolayers. This technique achieves a capacitance exceeding 2.8 μF cm−2, leakage currents around 10−7 A cm−2 and uniformity across a full wafer. Functional logic gates fabricated with these top-gate arrays underscore the route towards scalable, industry-compatible integration of high-κ films in 2D circuits.

Research from all publishers

Foundational work on scattering mechanisms in atomically thin semiconductors has clarified how ionised impurity scattering currently limits mobility in transition-metal dichalcogenide monolayers, while remote optical phonons from surrounding dielectrics will set the ultimate mobility ceiling at room temperature. The study identifies optimal dielectric environments to suppress scattering and approach intrinsic performance. A complementary approach embeds and patterns few-nanometre-thick high-κ oxides directly within van der Waals heterostructures using light-induced transformation. This nondestructive method allows the creation of flexible field-effect transistors, dual-gated devices and vertical tunnelling structures, as well as reversible filamentary memories, without degrading neighbouring 2D layers. Such patterned dielectrics open prospects for multifunctional, reconfigurable nanoelectronics.

Dielectric Engineering in Two-Dimensional Electronics publication trend

The graph below shows the total number of articles in dielectric engineering in two-dimensional electronics across all publications each year (not limited to Nature Index journals).

Technical terms

Dielectric constant (κ): A measure of a material’s ability to store electrical energy in an electric field relative to vacuum.

Van der Waals integration: The assembly of atomically thin layers via weak interlayer forces without chemical bonding.

Equivalent oxide thickness (EOT): The thickness of silicon dioxide that would produce the same capacitance as a given high-κ dielectric layer.

Subthreshold swing: The gate voltage required to increase the drain current by one order of magnitude in a FET, indicative of switching efficiency.

Field-effect transistor (FET): A transistor in which the current through a semiconducting channel is modulated by an electric field applied via a gate dielectric.

Interface state density (Dit): The number of electronic trap states per unit area per energy at the interface between a semiconductor and its gate dielectric.

References

1. Single-crystalline metal-oxide dielectrics for top-gate 2D transistors. Nature (2024).
2. Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration. Nature Communications (2023).
3. Charge Scattering and Mobility in Atomically Thin Semiconductors. Physical Review X (2014).
4. Laser-writable high-k dielectric for van der Waals nanoelectronics. Science Advances (2019).