Digital Pulse Width Modulation in Power Electronics

Digital pulse width modulation (DPWM) has become central to modern power conversion, enabling precise control of switching devices in DC–DC converters, inverters and motor drives. By moving the modulation process into the digital domain, designers can exploit high-speed processors and programmable logic to implement advanced timing schemes, adaptive control loops and real-time fault diagnostics. Digital implementations support sub-clock-period resolution, flexible carrier generation and integrated compensation algorithms, ensuring low output ripple, fast transient response and immunity to analogue drift. The rise of wide-bandgap semiconductors and multi-phase interleaved converters has driven switching frequencies into the multi-MHz range, placing stringent demands on DPWM resolution and latency. Contemporary research addresses these challenges by developing novel modulator architectures—such as cascaded delay-line schemes and dyadic fraction generators—to suppress limit-cycle oscillations and quantisation noise. At the system level, DPWM is now embedded within field-programmable gate arrays (FPGAs) and digital signal controllers, facilitating seamless integration with digital control laws, on-chip monitoring and adaptive dead-time management. This convergence of hardware and firmware is accelerating the deployment of highly efficient renewable-energy inverters, silicon-carbide DC–DC stages and automotive powertrains, underscoring the global significance of digital modulation technologies in enabling compact, intelligent and reliable power electronic systems.

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Research from all publishers

Recent work has demonstrated a dyadic DPWM scheme in a digitally controlled boost converter operating at 1.17 MHz. The dyadic approach suppresses limit-cycle oscillations and achieves over six-fold improvement in DC accuracy, while reducing output voltage ripple by approximately three times compared with conventional digital PWM with thermometric dithering. Both simulation and experimental results on a 7–10 V input, 13.8 V output stage validate the robustness of this method at high switching rates.

Advances in high-resolution DPWM architectures have been reported using single-path and cascaded delay-line designs implemented on an Artix-7 FPGA. These architectures decouple timing resolution from synthesis tool constraints, reaching a time granularity of 39 ps without raising the system clock frequency. A cascaded structure further allows resolution scaling or clock-frequency reduction as needed. Practical evaluation in a GaN-based synchronous buck converter confirms sub-nanosecond control of both duty cycle and dead time, with reproducible modulation across temperature and voltage variations.

A comparative study of digital PWM control strategies for high-power interleaved DC–DC converters has assessed three approaches—peak-current control, multi-sample averaged current control and enhanced single-sample averaging—on a 60 kW, 75 kHz silicon-carbide platform. The enhanced single-sample method offers the fastest dynamic response with acceptable noise immunity, while the multi-sample technique delivers the highest steady-state accuracy. Peak-current control provides the quickest transient reaction but exhibits stability limits around mid-range duty ratios, highlighting the trade-offs between speed, precision and robustness in digital control loops.

Digital Pulse Width Modulation in Power Electronics publication trend

The graph below shows the total number of articles in digital pulse width modulation in power electronics across all publications each year (not limited to Nature Index journals).

Technical terms

Digital Pulse Width Modulation (DPWM): A technique that generates switch-control signals by digitally comparing a reference word to carrier waveforms, enabling precise duty-cycle control and embedded compensation.

Dyadic Digital Pulse Width Modulator (DDPWM): A specialised DPWM variant using dyadic (binary fraction) increments to enhance timing resolution and mitigate limit-cycle oscillations in discrete-time control loops.

High-Resolution DPWM (HRDPWM): A DPWM architecture employing techniques such as cascaded delay lines or interpolated counters to achieve sub-clock-period timing precision, often in the picosecond range.

Limit-Cycle Oscillation (LCO): A self-sustaining oscillation in digital control systems caused by quantisation and sampling effects that can degrade regulation accuracy and induce ripple.

Field-Programmable Gate Array (FPGA): A reprogrammable semiconductor device comprised of logic blocks and interconnects, widely used to implement custom DPWM architectures with deterministic timing.

References

1. Limit-Cycle Free, Digitally-Controlled Boost Converter Based on DDPWM. IEEE Access (2023).
2. Single-Path High-Resolution Digital PWM Architectures With Cascadability of Delay Lines. IEEE Open Journal of Power Electronics (2024).
3. Comparison of digital PWM control strategies for high‐power interleaved DC–DC converters. IET Power Electronics (2018).