Dynamic Random Access Memory Reliability and Security

Dynamic random access memory (DRAM) underpins the bulk of modern computing systems by offering high density, low latency and cost-effectiveness. Its operation relies on storing charges in microscopic capacitors that must be periodically refreshed to prevent data loss. As device geometries shrink and densities rise, DRAM faces growing challenges in reliability, including cell leakage, disturbance errors and manufacturing defects, all of which can lead to spontaneous bit flips. Concurrently, a range of security threats has emerged, most notably the rowhammer phenomenon, wherein rapid repeated accesses to a row induce data corruption in adjacent rows through capacitive disturbance. Addressing these reliability and security concerns has become critical for data centres, mobile platforms and embedded systems. Researchers have pursued architectural defences such as targeted refresh strategies, on-die error-correction codes and built-in self-test mechanisms, while industry has explored redundancy schemes and enhanced fabrication processes. The global significance of this work is evident in applications from cloud infrastructure—where undetected memory errors can compromise large-scale services—to safety-critical systems in automotive and avionics, where fault tolerance is paramount. Advances now increasingly integrate cross-layer solutions that combine physical-level insights with system-level mitigation, ensuring that DRAM remains both dependable and secure as it continues to scale.

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Dynamic Random Access Memory Reliability and Security publication trend

The graph below shows the total number of articles in dynamic random access memory reliability and security across all publications each year (not limited to Nature Index journals).

Technical terms

Dynamic random access memory (DRAM): A semiconductor memory technology in which data are stored as electrical charges in capacitors and require periodic refresh to maintain integrity.

Rowhammer: A security vulnerability in DRAM where repeated accesses to a memory row induce bit flips in adjacent rows through capacitive disturbance.

Error-correction code (ECC): A method of detecting and correcting data errors in memory by adding redundant information during storage and retrieval.

Refresh cycle: A periodic operation in DRAM that restores charge in memory cells to prevent data loss due to leakage.

References

1. Rowhammer Attacks in Dynamic Random-Access Memory and Defense Methods. Sensors (2024).
2. On DRAM Rowhammer and the Physics of Insecurity. IEEE Transactions on Electron Devices (2021).
3. CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention. IEEE Access (2020).
4. Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement. IEEE Access (2021).
5. An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process. IEEE Access (2021).
6. OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems. Sensors (2021).
7. Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory. IEEE Access (2021).
8. Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors. Electronics (2018).