Efficient VLSI Architectures for Discrete Wavelet Transforms

Efficient VLSI architectures for the discrete wavelet transform (DWT) have become pivotal in enabling real-time signal and image processing across a range of applications, from high-definition video compression to wearable biomedical sensors. Contemporary designs exploit the lifting scheme to minimise arithmetic complexity and memory footprint, while achieving perfect reconstruction. Key strategies include pipelined and systolic array structures to increase throughput, folded and recursive modules to optimise area, and multiplier-less filter implementations to reduce power. Advances in hardware description languages and field-programmable gate arrays (FPGAs) facilitate rapid prototyping and energy-aware synthesis. Scaling multi-level transforms for two-dimensional image decomposition demands careful balancing of on-chip buffer sizes, critical-path delay, and hardware utilisation efficiency. Integrating clock-gating and dynamic reconfiguration further curtails dynamic power, making these architectures well suited to pervasive computing environments and high-performance codecs.

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Recent work has demonstrated a segmented modified fractional wavelet filter (SMFrWF) that divides each image line into segments to avoid repeated memory accesses. Implemented in HDL and prototyped on an FPGA, this architecture reduces time complexity by over 50% relative to conventional fractional filters and cuts energy consumption by nearly two-thirds under high-resolution workloads. A foundational study on multi-level lifting-based DWT proposes three hardware architectures—folded, pipelined and recursive—each optimising hardware utilisation efficiency through novel dual-input block designs. The pipelined variant attains single-adder critical paths for both (5,3) and (9,7) filters and employs clock-gating to slash power, while the recursive design halves multiplier count. More recently, a lifting-based fractional wavelet filter architecture (LFrWF) and its multiplier-less variant deliver substantial reductions in lookup tables, flip-flops and compute cycles when mapped to wearable sensor platforms. These designs exhibit up to 65% lower energy consumption compared with prior fractional approaches, validating the efficacy of multiplier-less lifting in resource-constrained VLSI implementations.

Efficient VLSI Architectures for Discrete Wavelet Transforms publication trend

The graph below shows the total number of articles in efficient vlsi architectures for discrete wavelet transforms across all publications each year (not limited to Nature Index journals).

Technical terms

Discrete Wavelet Transform (DWT): A mathematical operation that decomposes a signal into frequency subbands using scaled and translated wavelet functions.

Lifting Scheme: A factorisation method for computing the DWT in-place, reducing arithmetic operations and memory requirements.

Filter Bank: A collection of analysis and synthesis filters that separates a signal into subbands and reconstructs it perfectly.

Pipelining: A design technique that overlaps successive stages of computation to increase throughput in hardware implementations.

Field-Programmable Gate Array (FPGA): A reconfigurable device consisting of programmable logic blocks and interconnects used for prototyping and low-volume production.

Critical Path Delay: The longest combinational path between registers in a circuit, determining its maximum clock frequency.

Hardware Utilisation Efficiency: The ratio of active computational resources to the total resources available, reflecting design compactness.

References

1. SMFrWF: Segmented Modified Fractional Wavelet Filter: Fast Low-Memory Discrete Wavelet Transform (DWT). IEEE Access (2019).
2. High-performance hardware architectures for multi-level lifting-based discrete wavelet transform. EURASIP Journal on Image and Video Processing (2014).
3. Lifting‐Based Fractional Wavelet Filter: Energy‐Efficient DWT Architecture for Low‐Cost Wearable Sensors. Advances in Multimedia (2020).