Heterogeneous Integration in Advanced Packaging Technologies

Heterogeneous integration refers to the assembly of disparate semiconductor components—such as logic, memory and analogue dies—into a unified package, leveraging advanced interconnect and thermal-management schemes to overcome the limitations of monolithic scaling. By combining chiplets fabricated on different process nodes, materials and functions within a single system-in-package (SiP), designers achieve higher performance, lower power consumption and improved yield compared with traditional system-on-chip approaches. Key enabling platforms include two-and-a-half-dimensional (2.5D) integration using silicon or organic interposers, true three-dimensional (3D) stacking with through-silicon vias (TSVs), and fan-out wafer- and panel-level packaging (FOWLP/PLP) that create high-density redistribution layers without the cost and size constraints of large interposers. These multi-die assemblies support rapid prototyping, modular upgrades and heterogeneous material integration (for example, compound semiconductors or photonic elements) while delivering the signal bandwidth, thermal dissipation and form-factor advantages required by artificial intelligence, high-performance computing, mobile devices and the Internet of Things. Advances in industry standards for die-to-die interconnect, novel dielectric materials for redistribution layers and refined simulation of thermo-mechanical stresses are driving the maturation of these technologies from laboratory demonstrations to volume manufacture.

Research from Nature Portfolio

Recent studies have demonstrated the viability of universal chiplet interconnect express (UCIe) specifications for high-density, power-efficient 3D SiP designs. By reducing bump interconnect pitches down to one micrometre, researchers have shown that die-to-die signalling can approach or surpass the power-performance profile of a monolithic system-on-chip, provided the signalling frequency is optimally scaled. Architectural analyses reveal that die stacking with fine-pitch bumps achieves low latency and high reliability, and that advanced bump metallurgy and micro-bump array design minimise coupling losses and thermal hotspots. This work establishes a clear path towards ecosystem-level interoperability of heterogeneous chiplets from multiple suppliers, underpinned by open standards and compatible assembly processes.

Heterogeneous Integration in Advanced Packaging Technologies publication trend

The graph below shows the total number of articles in heterogeneous integration in advanced packaging technologies across all publications each year (not limited to Nature Index journals).

Technical terms

Heterogeneous integration: The assembly of different semiconductor dies and materials into a single package to enhance system performance and yield.

Chiplet: A modular die containing a specific function (for instance, CPU core or memory block) designed for integration with other chiplets.

System-in-Package (SiP): A packaging approach that combines multiple dies and passive components within a single enclosure, providing system-level functionality.

Interposer: An intermediate substrate—often silicon or organic—that hosts multiple dies and provides high-density interconnect routing.

Fan-Out Wafer-Level Packaging (FOWLP): A packaging technique that redistributes I/O pads beyond the original die footprint using moulded substrates and redistribution layers.

Through-Silicon Via (TSV): A vertical electrical interconnect passing through a silicon wafer or die, used for 3D stacking of devices.

References

1. High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express. Nature Electronics (2024).
2. Chiplet Heterogeneous Integration Technology—Status and Challenges. Electronics (2020).
3. Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration. Micromachines (2019).
4. Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions. Micromachines (2022).
5. Heterogeneous System Level Integration Using Active Si Interposer. IEEE Journal of the Electron Devices Society (2019).
6. A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates. Polymers (2023).