Low-Density Parity-Check Coding Techniques in Communication Systems
Summary
Low-density parity-check (LDPC) codes represent a class of forward error correction codes known for approaching the Shannon limit on channel capacity. Defined by sparse parity-check matrices, they enable iterative message passing between variable nodes and check nodes in a factor graph. Key decoding strategies include belief propagation and its approximations, such as the min-sum algorithm, which balance error-correction performance with computational complexity. LDPC codes are often instantiated in quasi-cyclic or protograph-based forms, facilitating hardware-friendly implementations and reduced memory requirements. These techniques underpin reliable data transmission across diverse media, from mobile broadband and satellite links to optical fibres and Internet-of-Things networks. Optimising LDPC encoder and decoder architectures—balancing throughput, latency and hardware efficiency—remains central to meeting evolving demands for high data rates and low-latency services in next-generation communication systems.
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Low-Density Parity-Check Coding Techniques in Communication Systems publication trend
The graph below shows the total number of articles in low-density parity-check coding techniques in communication systems across all publications each year (not limited to Nature Index journals).
Technical terms
Low-density parity-check (LDPC) code: An error-correcting code defined by a sparse parity-check matrix, enabling iterative message-passing decoding.
Parity-check matrix: A binary matrix whose null space defines valid codewords, with rows corresponding to parity constraints.
Belief propagation: An iterative algorithm for decoding LDPC codes, passing soft information between variable and check nodes to converge on a codeword.
Min-sum algorithm: An approximation of belief propagation that simplifies check-node operations by using the minimum of incoming messages.
Quasi-cyclic (QC): A structure for LDPC codes in which the parity-check matrix is composed of circulant submatrices, facilitating hardware implementation and reduced storage.
References
- An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA. Computers (2024).
- GPU-Based, LDPC Decoding for 5G and Beyond. IEEE Open Journal of Circuits and Systems (2021).
- Efficient QC-LDPC Encoder for 5G New Radio. Electronics (2019).
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