Low Noise Amplifier Design Techniques in CMOS Technology

Low noise amplifiers (LNAs) are critical components in the receiver front end of wireless systems, tasked with boosting weak signals while introducing minimal additional noise. Advances in complementary metal–oxide–semiconductor (CMOS) technology have enabled highly integrated, low-cost LNAs that serve applications ranging from 5G and millimetre-wave Internet-of-Things sensors to satellite navigation and radar. Key performance metrics include noise figure, gain, linearity and power consumption, all of which are interdependent and influenced by device parasitics and substrate losses at high frequencies. Designers have deployed a rich set of circuit techniques—input-matching networks, feedback loops, current-reuse structures, differential and cascode topologies, and body-biasing schemes—to optimise these figures of merit. More recent innovations exploit on-chip transformers, active inductors and noise-cancelling paths to extend bandwidth into the millimetre-wave band, while preserving low noise figure and high gain. Current trends focus on multi-band and reconfigurable LNAs that accommodate emerging standards, as well as low-power architectures suited to battery-operated platforms. The convergence of advanced CMOS nodes and novel circuit-level strategies continues to push the frontiers of noise performance, system integration and energy efficiency in modern communication and sensing networks.

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Low Noise Amplifier Design Techniques in CMOS Technology publication trend

The graph below shows the total number of articles in low noise amplifier design techniques in cmos technology across all publications each year (not limited to Nature Index journals).

Technical terms

Noise Figure (NF): A measure (in decibels) of the degradation of signal-to-noise ratio introduced by an amplifier.

Transconductance (gm): The ratio of output current change to input voltage change in a transistor, a key determinant of gain.

Cascode Topology: A two-transistor configuration combining common-source and common-gate stages to enhance gain, isolation and bandwidth.

Noise Cancellation: A technique that subtracts correlated noise contributions from parallel amplifier paths to lower the overall noise figure.

Input Matching: The design of networks (inductive, capacitive or transformer-based) to present the desired source impedance to the amplifier input, maximising power transfer and minimising reflections.

References

1. CMOS low noise amplifier design trends towards millimeter-wave IoT sensors. Ain Shams Engineering Journal (2024).
2. A 0.02–4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse. IEEE Journal of Solid-State Circuits (2020).
3. A 22.9–38.2-GHz Dual-Path Noise-Canceling LNA With 2.65–4.62-dB NF in 28-nm CMOS. IEEE Journal of Solid-State Circuits (2021).