Low-Power SRAM Design Techniques for Nanoscale Technologies

Static random-access memory (SRAM) remains a cornerstone of modern digital systems, yet aggressive downscaling into the sub-10 nm regime poses acute challenges in leakage control, variability management and energy efficiency. At the device level, innovations range from multigate FinFET cells and tunnelling-based diodes to carbon-nanotube FET bit-cells, each seeking to reduce standby current and enhance noise immunity. Circuit-level strategies include near-threshold and sub-threshold supply operation, dynamic voltage scaling, adaptive body biasing and error-detecting pads to trim margins without jeopardising performance. Architectural solutions exploit multiported and standard-cell memory macros, sleep transistors and bit-interleaved layouts to curtail dynamic and leakage power across diverse workloads. Collectively, these techniques enable ultralow-power operation for battery-powered IoT nodes, on-chip caches and wearable processors, balancing retention time, access speed and resilience in the nanoscale era.

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Low-Power SRAM Design Techniques for Nanoscale Technologies publication trend

The graph below shows the total number of articles in low-power sram design techniques for nanoscale technologies across all publications each year (not limited to Nature Index journals).

Technical terms

SRAM: Static random-access memory storing bits in cross-coupled inverters without the need for refresh, valued for fast access but prone to leakage.
Near-threshold operation: Running supply voltage close to transistor threshold to minimise dynamic power while increasing susceptibility to variation.
Static noise margin (SNM): The maximum noise voltage a cell can tolerate without flipping, indicating read and hold robustness.
Negative differential resistance (NDR): A characteristic in which an increase in voltage reduces current, harnessed in tunnelling devices to lower leakage.
Bit-interleaved structure: A layout technique distributing bits of a word across multiple sub-cells to alleviate half-select stress and improve stability.

References

1. Silicon cross-coupled gated tunneling diodes. Chip (2024).
2. Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation. IEEE Access (2021).
3. Design and Performance Analysis of 32 × 32 Memory Array SRAM for Low-Power Applications. Electronics (2023).
4. Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. IEEE Access (2023).
5. Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM. Journal of Nanotechnology (2017).