N-Path Filter Applications in RF Receiver Design

N-path filters exploit periodic switching of capacitors or inductors across multiple parallel paths to achieve high‐quality‐factor, tunable bandpass responses directly at radio frequencies. By distributing the signal in time rather than relying on bulky passive resonators, these filters enable on‐chip preselection and image rejection without degrading noise figure or linearity. In mixer‐first or passive‐mixer‐first receiver architectures, N-path filtering precedes low‐noise amplification, offering narrowband selectivity that tracks local‐oscillator frequency and suppresses out-of-band interferers. Discrete-time and delta-sigma approaches further integrate N-path principles into digital loops, allowing reconfigurable centre frequencies, adjustable bandwidths and deep stopband attenuation through switched‐capacitor networks. Across emerging 5G/6G front ends, Internet-of-Things modules and satellite links, N-path filters provide a compact, low-power route to high selectivity, superior blocker tolerance and simplified calibration, thereby enabling widely tunable, high-performance receivers in advanced CMOS technologies.

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Generalised sequence-mixing N-path architectures have been demonstrated to support dynamic frequency and spatial filtering in wideband, interferer-tolerant receivers. By reconfiguring switching sequences and phase offsets across multiple paths, these designs achieve simultaneous blocker rejection and channelisation without external filters, extending operation into millimetre-wave bands with minimal additional power.

A discrete-time delta-sigma direct RF-to-digital receiver applies N-path mixing within its feedback loop, using a passive mixer array and reconfigurable passive/active filters to shape the signal prior to quantisation. Sampling at a sub-harmonic of the local-oscillator, this architecture attains high-Q bandpass filtering, relaxed linearity demands on the RF amplifier and an overall dynamic range exceeding 80 dB, while consuming under 50 mW in 65 nm CMOS.

A tutorial on high-intermediate-frequency discrete-time receivers clarifies how aliasing trade-offs govern N-path filter performance in IoT applications. It shows that careful selection of switching rate, decimation factor and capacitor ratios determines both in-band flatness and stopband rejection. This work lays a foundation for optimising power consumption and interference immunity in compact, tuneable front ends.

N-Path Filter Applications in RF Receiver Design publication trend

The graph below shows the total number of articles in n-path filter applications in rf receiver design across all publications each year (not limited to Nature Index journals).

Technical terms

N-path filter: A switched‐capacitor or switched‐inductor network that feeds N parallel branches in turn, synthesising a bandpass response with high quality factor and tunable centre frequency.

Passive-mixer-first receiver: An RF front end where the input signal is first down-converted by a passive mixer array before any active amplification or filtering, enabling on-chip N-path preselection.

Discrete-time filtering: The process of shaping a signal’s spectrum by periodically sampling and integrating it using switched capacitors, often implemented within delta-sigma loops.

Quality factor (Q): A measure of filter selectivity defined as the ratio of centre frequency to bandwidth; high-Q filters offer narrow passbands and strong interference rejection.

Aliasing: Undesired spectral folding that occurs when sampling a signal below twice its bandwidth, mitigated in N-path designs by careful choice of switching frequency and decimation schemes.

References

1. A Passive-Mixer-First Acoustic-Filtering Superheterodyne RF Front-End. IEEE Journal of Solid-State Circuits (2021).
2. A Four-Phase Passive Mixer-First Receiver With a Low-Power Complementary Common-Gate TIA. IEEE Access (2020).
3. A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications. IEEE Journal of Solid-State Circuits (2023).
4. Design of High-IF Discrete-Time Receivers for IoT: Demystifying Aliasing Trade-Offs. IEEE Transactions on Circuits & Systems II Express Briefs (2022).
5. A Highly Flexible Passive/Active Discrete-Time Delta-Sigma Receiver. Electronics (2024).
6. Recent Developments in Integrated Interferer-Tolerant Receivers for Reconfigurable Radios. IEEE Journal of Microwaves (2021).