Negative Bias Temperature Instability in CMOS Technologies

Negative Bias Temperature Instability (NBTI) is a critical reliability concern in complementary metal–oxide–semiconductor (CMOS) devices, manifesting as a progressive shift in the threshold voltage of p-channel transistors under negative gate bias at elevated temperature. This phenomenon arises from the generation and trapping of interface states and charges within the gate dielectric, leading to increased device delays, timing violations and potential functional failures over the operational lifetime. As device dimensions shrink into the deep-nanoscale regime and high-κ dielectrics replace silicon dioxide, NBTI mechanisms evolve, with stress bias, temperature excursions and material interfaces exerting a combined influence on degradation kinetics and recovery behaviour. The cumulative impact of NBTI is felt across digital and analogue circuits alike, from logic paths in microprocessors to memory arrays in system-on-chip designs. Practical mitigation strategies range from process adjustments—such as annealing optimisations and gate stack engineering—to circuit-level techniques, including adaptive voltage scaling, power gating and run-time monitoring. Understanding the interplay between device physics and system architecture is essential to ensure robust performance in applications spanning automotive electronics, 5G communications and edge computing.

Research from Nature Portfolio

No recent Nature Portfolio content available.

Research from all publishers

Recent studies have advanced online monitoring of NBTI by leveraging existing power-gating infrastructure. A coarse-grained technique exploits standby discharge timing to infer threshold voltage shifts without additional sensors, achieving sub-6 per cent estimation error in simulation and experimental validation on 65 nm CMOS chips. In parallel, experimental work on p-channel FinFETs with atomic layer deposition tungsten gate filling demonstrates that post-metallisation annealing can reduce fresh interface trap density by over 30 per cent and improve voltage overdrive by nearly 29 per cent. By analysing trap generation and recovery kinetics under varied bias and temperature conditions, the study identifies optimal annealing parameters that substantially alleviate NBTI degradation. Complementing these device-level advances, an embedded real-time reliability prediction circuit integrates NBTI sensors within the chip, providing continuous online diagnostics and early warning of reliability hazards. This compact IP-core approach offers direct measurement of stress-induced threshold shifts and temperature effects in situ, enabling dynamic adaptation of operating conditions to preserve performance and extend lifetime. Together, these contributions illustrate a multi-tiered strategy—spanning process, device and system levels—to monitor, model and mitigate NBTI in modern CMOS technologies.

Negative Bias Temperature Instability in CMOS Technologies publication trend

The graph below shows the total number of articles in negative bias temperature instability in cmos technologies across all publications each year (not limited to Nature Index journals).

Technical terms

Negative Bias Temperature Instability (NBTI): A degradation mechanism in p-channel transistors where negative gate bias and elevated temperature induce interface trap generation and charge trapping, causing threshold voltage shifts and slower device operation.

Threshold Voltage (VT): The gate-to-source voltage at which a transistor channel begins to conduct; shifts in VT due to NBTI lead to timing errors and reduced drive current.

Gate Oxide: The insulating dielectric layer between the transistor gate and channel; its quality and thickness critically influence NBTI-induced trap formation.

Fin Field-Effect Transistor (FinFET): A three-dimensional transistor architecture with a thin silicon fin as the channel, offering improved control of short-channel effects but introducing new NBTI considerations at fin surfaces.

Annealing Process: A thermal treatment applied after metallisation to repair interface defects and reduce trap densities in the gate stack, thereby mitigating threshold voltage degradation.

Power Gating: A circuit-level technique that switches off idle blocks to reduce leakage; can be repurposed to monitor NBTI by observing changes in power-network discharge characteristics.

References

1. Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2017).
2. Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization. IEEE Journal of the Electron Devices Society (2021).
3. Real-Time Monitoring Method and Circuit Based on Built-In Reliability Prediction. Micromachines (2024).