Network-on-Chip Architectures and Design Techniques

Network-on-chip (NoC) paradigms have emerged as the de facto interconnection strategy for modern many-core and multiprocessor systems-on-chip, addressing the limitations of bus-based designs through scalable, packet-switched fabrics. Architectures range from canonical regular meshes and tori to more exotic circulant and hierarchical topologies, each offering distinct trade-offs in latency, throughput, power consumption and implementation complexity. Router microarchitectures underpin these fabrics, with innovations in virtual channel allocation, switch arbitration and fault-tolerant pipelines enhancing reliability under deep-submicron scaling. At the system level, application mapping techniques strive to place communicating tasks to minimise hop count and energy usage, while adaptive routing algorithms dynamically steer traffic around congested or faulty regions. Emerging wireless network-on-chip (WNoC) solutions leverage on-chip antennas and millimetre-wave links to bypass multi-hop limitations, and recent breakthroughs in programmable metasurfaces promise to sculpt on-chip electromagnetic environments for pulse-shaped channels. Taken together, these advances forge a rich design space, balancing performance, power and area in the pursuit of ever-denser integration and energy-efficient computation.

Research from Nature Portfolio

No recent Nature Portfolio content available.

Research from all publishers

Recent evaluations of application mapping strategies have provided a systematic comparison of bio-inspired, greedy and hybrid algorithms, revealing that optimised task-to-core assignments can reduce communication cost and latency by up to 30 percent, while cutting energy consumption in embedded multimedia benchmarks. A comprehensive survey of chip-scale wireless channels has characterised propagation at millimetre-wave and terahertz bands, identifying key design drivers such as on-chip multipath, package effects and antenna-wire interactions. This work lays the groundwork for practical WNoC deployments by supplying empirical models and highlighting the challenges of link reliability and co-integration with dense interconnect layers. Building on this foundation, a novel metasurface-programmable WNoC architecture demonstrates how reconfigurable intelligent surfaces embedded within the chip can equalise impulse responses, enabling higher modulation speeds without sacrificing signal strength. Experimental results indicate that such programmability can halve inter-core latency in wireless links and open avenues for dynamic, software-driven on-chip communication fabrics.

Network-on-Chip Architectures and Design Techniques publication trend

The graph below shows the total number of articles in network-on-chip architectures and design techniques across all publications each year (not limited to Nature Index journals).

Technical terms

Network-on-Chip (NoC): A packet-switched interconnect framework for on-chip communication among multiple processing elements.

Mesh Topology: A regular arrangement of routers in a two-dimensional grid, offering simple layout and predictable routing hops.

Circulant Topology: A graph-based network structure with analytically defined long-range links that can reduce diameter and average path length.

Application Mapping: The assignment of computational tasks to specific cores to minimise communication overhead and energy consumption.

Routing Algorithm: A policy determining the path that packets follow through the NoC, including deterministic, adaptive and congestion-aware schemes.

Wireless Network-on-Chip (WNoC): An NoC variant employing on-chip antennas and radio links to complement or replace wired channels for long-range communication.

Reconfigurable Intelligent Surface (RIS): A metasurface with tunable elements that can shape electromagnetic wavefronts to optimise channel characteristics.

Virtual Channel: A logical buffering lane within a router input port that prevents head-of-line blocking and improves throughput.

References

1. Networks on Chips: Structure and Design Methodologies. Journal of Electrical and Computer Engineering (2011).
2. Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs. IEEE Access (2020).
3. Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey From Millimeter-Wave to Terahertz and Optics. IEEE Access (2019).
4. Metasurface‐Programmable Wireless Network‐On‐Chip. Advanced Science (2022).
5. NoCGuard: A Reliable Network-on-Chip Router Architecture. Electronics (2020).