Power Device Engineering and Semiconductor Technologies

Power device engineering encompasses the design, fabrication and optimisation of semiconductor components capable of handling high voltages and currents with minimal losses. Central to this field are lateral and vertical power MOSFET architectures, particularly laterally diffused metal–oxide–semiconductor (LDMOS) devices, superjunction structures and drift-region engineering. Recent strides in wide-bandgap materials, notably silicon carbide (SiC) and gallium nitride (GaN), have extended operational limits in terms of breakdown voltage, thermal stability and switching speed. Advanced dielectric integration—such as high-k gate oxides and field plates—permits improved electric-field modulation, reducing specific on-resistance while preserving avalanche ruggedness. Concurrent progress in wafer bonding and substrate innovation has enabled Si/SiC heterostructures that combine the maturity of silicon processing with the thermal resilience of SiC. These developments drive global applications in renewable energy conversion, electric vehicles and industrial motor drives, where efficiency gains translate directly into reduced energy consumption and enhanced system reliability.

Research from Nature Portfolio

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Research from all publishers

Innovations in channel doping have been demonstrated to boost ON-state performance and reliability of LDMOS transistors without additional process cost. By introducing a graded P-well mask alignment, drive capability gains of around 30% and improved hot-carrier robustness have been achieved while maintaining off-state characteristics. A novel lateral double-diffused MOS structure with triple-direction high-k gate and field dielectrics has been proposed, surrounding silicon pillars with high-k material to increase gate capacitance, broaden channel width and enhance breakdown voltage simultaneously, delivering up to 48% reduction in specific on-resistance and a 157% rise in breakdown. Advanced RESURF-based drain-extended MOS architectures integrate surface implants, split gates and shallow trench isolation to reduce gate charge and enhance avalanche ruggedness, achieving over 65% improvement in high-frequency figure-of-merit and extended safe operating area under inductive switching conditions.

Power Device Engineering and Semiconductor Technologies publication trend

The graph below shows the total number of articles in power device engineering and semiconductor technologies across all publications each year (not limited to Nature Index journals).

Technical terms

LDMOS: Laterally diffused metal–oxide–semiconductor transistor featuring a drift region for high-voltage operation.

Specific on-resistance (R_ON,sp): The resistance per unit area of a device in the on state, inversely related to conduction efficiency.

Breakdown voltage (BV): The maximum voltage a device can block in off state before avalanche conduction occurs.

RESURF: Reduced surface field technique employing implants or field plates to optimise electric-field distribution.

High-k dielectric: A material with high dielectric constant used to increase gate capacitance and control electric field in transistors.

References

1. A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors. IEEE Journal of the Electron Devices Society (2021).
2. Novel LDMOS With Integrated Triple Direction High-k Gate and Field Dielectrics. IEEE Transactions on Electron Devices (2021).
3. Development, characterisation and simulation of wafer bonded Si-on-SiC substrates. Materials Science in Semiconductor Processing (2018).
4. Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability. IEEE Access (2021).