Through-Silicon Via Reliability in 3D Integrated Circuits

Through-silicon vias (TSVs) are vertical interconnects that enable high-density stacking of semiconductor dies in three-dimensional integrated circuits (3D ICs). Their reliability underpins the performance, yield and lifespan of advanced computing and memory systems. Key failure modes include electromigration-induced voiding, dielectric breakdown, liner delamination and fatigue cracking driven by thermal cycling and mechanical stress. As device scaling drives higher current densities and tighter thermal budgets, these stresses accelerate material degradation and interfacial failure. Reliability enhancement strategies focus on optimising TSV geometry, integrating multilayer barriers, developing stress-compliant liners and applying novel thermal annealing schemes. In parallel, machine-learning-based predictive models and in situ monitoring techniques are emerging to assess TSV health and guide design-level mitigation. A robust understanding of failure mechanisms and innovative countermeasures is critical for maintaining signal integrity, minimising downtime and realising the full potential of 3D IC architectures in high-performance computing, mobile devices and heterogeneous systems.

Research from Nature Portfolio

Recent studies have showcased in situ synchrotron X-ray tomography to monitor void evolution in TSV liners under repeated thermal cycling, revealing nanoscale coalescence pathways that inform optimised annealing protocols. Another investigation introduced a multilayer barrier scheme combining tantalum-based metallic liners with self-healing polymer fillers, substantially reducing electromigration-driven failures by accommodating thermal expansion mismatch. A third work employed deep-learning-driven predictive models to forecast TSV fatigue lifetimes under complex temperature-current profiles, enabling adaptive stress management in 3D IC designs.

Research from all publishers

A thermal-aware online fault-tolerance method dynamically reallocates redundant TSVs within a 3D network-on-chip according to real-time temperature data, enhancing mean time to failure without excessive redundancy overhead. Advances in built-in self-test (BIST) architectures now permit simultaneous detection and classification of resistive-open and leakage faults within a single clock cycle, optimising test time and power consumption. Complementary work proposes a switch-matrix repair scheme tailored to clustered TSV faults, achieving high repair yields with minimal area and delay penalties by strategic grouping of spare TSVs.

Through-Silicon Via Reliability in 3D Integrated Circuits publication trend

The graph below shows the total number of articles in through-silicon via reliability in 3d integrated circuits across all publications each year (not limited to Nature Index journals).

Technical terms

Through-Silicon Via (TSV): A vertical electrical interconnect passing through a silicon wafer to connect stacked dies in 3D ICs.

Electromigration: Movement of metal atoms under high current densities, causing void formation and open-circuit failures in interconnects.

Thermal Cycling: Repeated heating and cooling that generates mechanical stress due to mismatched thermal expansion among materials.

Built-in Self-Test (BIST): On-chip testing circuitry enabling automated detection and diagnosis of interconnect faults without external equipment.

Self-healing Polymer Liner: A compliant polymer layer designed to fill microvoids and mitigate stress within TSV barrier structures, improving mechanical integrity.

References

1. A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems. IEEE Access (2020).
2. A TSV Test Method for Resistive Open Fault and Leakage Fault Coexisting. IEEE Access (2021).
3. Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults. IEEE Access (2025).