VLSI Floorplanning Optimization Techniques

Very-large-scale integration (VLSI) floorplanning is the process of arranging functional modules within the chip’s physical boundary to satisfy performance, area and interconnect requirements. As a combinatorial and NP-hard problem, floorplanning demands efficient approaches that can explore vast search spaces and balance multiple criteria such as chip area, total wirelength, power consumption, thermal distribution and timing constraints. Classical exact methods ensure optimality for small circuits but do not scale, whereas heuristic and metaheuristic methods—such as simulated annealing, genetic algorithms, particle swarm optimisation and hybridised swarm-intelligence techniques—offer practical trade-offs between solution quality and runtime. Floorplan representations, including slicing structures (binary trees) and non-slicing schemes (corner lists, B*-trees, sequence pairs), heavily influence the search dynamics and the ease of applying constraints like fixed outline or multiple supply voltages. Recent advances have also explored the integration of machine learning, particularly reinforcement learning, to guide placement decisions, as well as novel penalty functions and multi-objective frameworks that reconcile conflicting targets. The global significance of these developments is evident in the improved manufacturability, yield and energy efficiency of modern microprocessors, system-on-chips and emerging 3D integrated circuits.

Research from Nature Portfolio

No recent Nature Portfolio content available.

Research from all publishers

A hybrid metaheuristic combining ant colony optimisation with a firefly algorithm has been shown to deliver consistent reductions in chip area, total wirelength and peak temperature. By using ant colony strategies to seed an initial population of high-quality solutions and then refining them with firefly movements, the technique achieves multi-criteria optimisation on benchmark circuits, demonstrating improvements over standalone methods in layout density and thermal balance.

An improved simulated annealing framework introduces a two-stage penalty function to handle fixed-outline constraints more effectively. The first stage ensures feasibility by preventing modules from exceeding the prescribed boundary, while the second stage guides modules towards optimal positions near constraint edges. This approach achieves a 100 percent success rate on standard benchmarks with significant wirelength and area improvements at varying aspect ratios.

Deep reinforcement learning has recently been applied to the sequence-pair representation of floorplans, treating placement as a sequential decision-making task. An agent explores permutation spaces and receives feedback on area, interconnect length and overlap penalties. On standard test suites, the learned policy outperforms conventional search heuristics, offering a scalable route to automated floorplan generation for complex highly integrated designs.

VLSI Floorplanning Optimization Techniques publication trend

The graph below shows the total number of articles in vlsi floorplanning optimization techniques across all publications each year (not limited to Nature Index journals).

Technical terms

Floorplanning: The step in VLSI physical design that determines module placement within a chip boundary to optimise area, interconnect and performance.

Metaheuristic algorithm: A high-level approach that guides subordinate heuristics to explore search spaces and escape local optima, commonly used for NP-hard problems.

Sequence-pair representation: A non-slicing encoding of module order using two permutations, which defines relative positions without hierarchical cuts.

Simulated annealing: A global optimisation technique inspired by material annealing, using probabilistic acceptance of worse solutions to avoid local minima.

NP-hard problem: A classification indicating that no known polynomial-time algorithm can solve all instances optimally, necessitating approximate or heuristic solutions.

References

1. A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems. IEEE Access (2023).
2. An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning. IEEE Access (2020).
3. A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence Pairs †. Applied Sciences (2024).