Introduction

Short wavelength infrared (SWIR) photodetection technology ranging from 1 to 2.5 μm plays a crucial role in various applications including night vision, remote sensing and optical communication due to its excellent transmission capabilities under harsh atmospheric conditions such as heavy dust or dense fog1,2,3,4,5,6. As the demand for next-generation high-performance photodetectors continues to grow, there has been increasing interest in the development of advanced SWIR sensors7,8,9,10,11. Currently, commercial SWIR photodetectors are primarily fabricated using indium gallium arsenide (InGaAs)12,13,14,15 and mercury Cadmium Telluride (HgCdTe)16,17,18. However, InGaAs-based devices require high-cost epitaxial growth techniques such as molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE) and metal-organic chemical vapor deposition (MOCVD)2. HgCdTe material also suffers from toxicity, high cost, complex material growth techniques and cooling system requirements1,19. To overcome these limitations, Collolidal quantum dots (CQDs), leading material for next-generation thin films, have recently emerged as a key component in SWIR sensors due to their size-tunable absorption spectra and facile fabrication20,21. In this regard, various studies have been conducted on CQDs, including PbS9,22,23 and PbSe24,25. However, CQD-based photodetectors typically exhibit peak-valley-like absorption, which limits broadband detection over a wide spectral range and based on heavy metals such as Pb and Hg, which are regulated under the Restriction of Hazardous Substances (RoHS)9,10. These limitations highlight the need for low-cost, scalable and environmentally friendly SWIR photodetector materials.

Recently, tellurium (Te), a low-dimensional material, has garnered significant attention for its potential in SWIR photodetection26,27,28. Te exhibits a tunable bandgap ranging from 1.3 to 0.35 eV, depending on its thickness, due to quantum confinement effects and demonstrates high absorption in the SWIR range29,30,31,32,33,34,35,36,37. Te also possesses excellent charge carrier transport characteristics, making it a suitable material for high-performance transistor applications38,39,40,41,42,43,44. In transistor applications, achieving a low off current (Ioff) requires reducing the Te layer thickness to 10 nm or less, which increases the bandgap to approximately larger than 0.7 eV. However, decreasing the film thickness significantly reduces SWIR absorption due to the reduction of interaction length between the light and the material, introducing a fundamental trade-off between electrical performance and optical absorption. To address this issue, Tellurium-Selenium (Te-Se) alloys were recently utilized to modulate the bandgap45,46, enabling both high transistor performance47,48,49,50 and effective SWIR photodetectio50,51,52,53,54. Since, Se has a similar crystal structure with Te, it readily forms alloys, allowing bandgap modulation while preserving the crystal structure and maintaining a balance between electrical and optical properties48.

Furthermore, a dual-gate (DG) device architecture combining the functionalities of a photodiode and a phototransistor could be introduced to enhance photoresponse characteristics55,56,57,58,59. However, there has been few research on SWIR photodetection for dual-gate-based Te-Se alloy-based TFT devices while maintaining the maximum transmittance of the top electrode.

In this study, the Te0.7Se0.3 alloy-based dual-gate phototransistor utilizing Indium Tin Oxide (ITO) as the top gate was proposed, which exhibits ~ 77% SWIR absorption, optimizing light interaction within the device. The optimized dual-gate TFT device shows the electrical performance with a field-effect mobility of 3.8 cm− 1- V− 1s− 1 and subthreshold swing of 1.9 V/dec. by minimizing interface charge scattering owing to the introduction of SiO2 interfacial layer. Furthermore, in this structure, the bottom gate is negatively biased to induce a p-type channel, while the top gate is positively biased to form an n-type channel, effectively facilitating charge carrier separation. This built-in field significantly improve photogenerated electron-hole pairs collection efficiency, achieving a responsivity of 559.3 A/W and a specific detectivity of 1.91 × 1011 Jones at 1300 nm wavelength.

Methods

Films preparation

Te and Se targets (99.99%, Itasco) were used to deposit Te and Te0.7Se0.3 alloy thin films at room temperature using RF magnetron sputtering. The base pressure in the RF magnetron sputtering chamber was maintained at 5.0 × 10− 6 Torr and the working pressure was adjusted to 10 mTorr by supplying 20 sccm of Ar gas (99.99%). For Te thin film deposition, an RF power of 20 W was applied to the Te target and for Te0.7Se0.3 alloy thin film deposition, an RF power of 20 W was applied to each of the Te and Se targets. Before deposition, pre-sputtering was performed for 5 min and the Te thin film was deposited by sputtering for 38 s and the Te0.7Se0.3 alloy thin film for 20 s. The deposited Te and Te0.7Se0.3 alloy thin films were annealed on a hotplate set at 200 °C for 15 min under an air atmosphere. Plasma-enhanced ALD using trimethylaluminum (TMA) and oxygen plasma as Al precursor and oxidant was used to deposit 25 nm Al2O3 films at 200 °C under 1.5 Torr. The TMA and O2 flows were 50 sccm respectively and the plasma power was 150 W. In addition, a SiO2 target was used to deposit 5 nm SiO2 thin films at room temperature using RF magnetron sputtering. The base pressure in the RF magnetron sputter chamber was maintained at 1.0 × 10− 6 torr and a working pressure of 20 mTorr was maintained using 25 sccm of Ar gas (99.99%). The RF power was 20 W applied to the SiO2 target. Pre-sputtering was performed for 10 min and then SiO2 thin films were deposited by sputtering for 15 min. 25 nm Al2O3 thin films were deposited under 150 °C, 1.5 torr using ALD with TMA and H2O for passivation and top gate dielectric. TMA, O2 flow was 50 sccm respectively. ITO was deposited using direct current (DC) magnetron reactive sputtering with an ITO target composition of In2O3:SnO2 = 90:10 wt%. The deposition temperature, sputtering power and working pressure were set to 150 °C, 150 W and 3.5 mTorr, respectively. The oxygen flow ratio (O2 / O2 + Ar) was varied from 0 to 0.011.

Device fabrication

The 300 nm SiO2/P⁺⁺ substrate was cleaned with acetone, methanol and isopropyl alcohol (IPA) for 5 min each using an ultrasonic cleaner. The SiO2 was then patterned for the dry etch process and reactive ion etching (RIE) using Ar and CF4 gases was used to form 90 nm deep SiO2 trenches. To form the buried bottom gate, 90 nm Ni was then deposited using electron beam evaporation and a lift-off process was performed. The gate dielectric was deposited using 25 nm Al2O3 and 5 nm SiO2 using atomic layer deposition (ALD) and RF magnetron sputtering, respectively. Subsequently, Te and Te/Se alloy thin films were deposited by RF magnetron sputtering for channel formation and then annealed for 15 min under an air atmosphere on a hotplate set at 200 °C. The patterning process was performed to define the channel area using RIE with Ar gas. After stripping the photoresist, it was patterned to form the source/drain electrodes and 60 nm Ni was deposited using electron beam evaporation and a lift-off process was performed. In addition, 25 nm Al2O3 was deposited at 150 °C using ALD for passivation and top gate dielectric formation. Finally, ITO was deposited using RF magnetron sputtering after patterning to form the top gate and the photoresist was stripped.

Material characterization

To analyze the crystal structure, focused ion beam (FIB, NX2000, Hitachi) and scanning transmission electron microscope (STEM, JEM-ARM300F, JEOL) were used to obtain FFT patterns, TEM, HR-TEM and HR-STEM images and elemental mapping was performed using an energy dispersive X-ray spectroscopy (EDS) detector attached to the STEM. X-ray diffraction (XRD, EMPYREAN, Malvern Panalytical) was also used to further analyze the crystal structure. UV-vis-NIR spectroscopy (Cary 5000 UV-Vis-NIR, Agilent) was used to analyze the transmittance of ITO, transmittance, reflectance and absorbance of Te and Te/Se alloy films. Raman spectra were obtained using a 532 nm excitation laser raman system (XperRAM-CS, NANOBASE). The surface morphology and roughness of the Te/Se thin films were analyzed using Atomic force microscopy (AFM, NX10, Park systems). Chemical bonding and composition were analyzed using X-ray photoelectron spectroscopy (XPS, NEXSA, Thermo Fisher Scientific). Optical images of the devices were captured using optical microscopy (OM, OPTIC-CX40M-TR, Optic Korea).

Electrical and optical characterization

The optical properties were measured under the illumination of LEDs (M1050L4, M1200L4 and M1300L4, THORLABS) with wavelengths of 1050, 1200 and 1300 nm. A power meter was used to determine the illumination power intensity (P). All measurements were performed in air at room temperature.

Results

Device structure and operation principle of dual-gate Te/Se phototransistor

Figure 1a illustrates the dual-gate phototransistor device structure with a Te/Se channel layer and Ni and ITO as bottom and top gates, respectively. The incident light (SWIR light source, LED) covers the entire device and illuminates it vertically from above. The detailed device fabrication process is outlined in Figure S1 (Supporting Information). Figure 1b shows the schematic crystal structure of the Te/Se alloy thin film in this study. It shows the fundamental one-dimensional (1D) helical chain structure and it can be seen that the chains of Te atoms are stacked together in a hexagonal array through van der Waals forces48,53. Te and Se have similar crystal structures, with Se atoms partially substituting for Te atoms within the lattice48,54. An optical image of a dual-gate phototransistor device based on Te/Se alloy thin film is shown in Fig. 1c. The fabricated device has an active area defined by a channel length (L) of 2\(\:{\upmu\:}\text{m}\) and a width (W) of 3\(\:{\upmu\:}\text{m}\), corresponding to 6\(\:{\upmu\:}\text{m}\)2, which was used for the responsivity and specific detectivity calculations. Nickel (Ni), with a high work function of approximately 5.0 eV, was used for the source and drain electrodes.

Figure 1d shows a simplified illustration of the operating mechanisms comparing with a single-gate and a dual-gate phototransistor, respectively. In a single gate phototransistor (left side), incident light (SWIR light source) generates electron-hole pairs within the semiconductor channel layer. These charge carriers are then separated, with one type of carrier (holes) transported toward the drain, thereby inducing a photocurrent. On the other hand, in a dual-gate phototransistor (right side), when the top and bottom gates are biased of opposite polarities, the semiconductor channel layer can form p-type and n-type channels. Therefore, when light is absorbed, electron-hole pairs are generated in the semiconductor layer and generate an electric field equal to the built-in field of the diode to separate the electrons-holes, causing two types of carriers transported toward the drain and source, respectively. This mechanism leads to improved photocurrent in dual-gate phototransistors compared to single gate phototransistors56,57,59.

The light transmission of the top gate plays a crucial role in enabling light to reach the semiconductor layer for effective photocurrent generation. To enhance transmission in the SWIR range, the oxygen partial pressure (O2 / O2 + Ar) during the deposition of the top gate ITO was optimized. As shown in Fig. 1e and Figure S2, the SWIR transmittance increases with rising oxygen partial pressure from 0 to 0.011. This behavior can be attributed to changes in carrier concentration within the ITO film. Electrons originating from oxygen vacancies and Sn4+ ions substituted at In3+ sites decrease as more oxygen are incorporated into the lattice (i.e., as the oxygen partial pressure increases), leading to a reduction in carrier concentration60. Since SWIR transmittance is closely related to carrier concentration, this effect can be further explained by the plasma wavelength that separates the reflection region from the transmission region61. The plasma wavelength was calculated using the following Eq. 61.

$$\:{\lambda\:}_{p}=2\pi\:C{\left(\frac{{\epsilon\:}_{0}{\epsilon\:}_{\infty\:}{m}^{*}}{{e}^{2}N}\right)}^{1/2}$$
(1)

Here \(\:C\), \(\:{m}^{*}\),\(\:\:{\epsilon\:}_{0}\), \(\:{\epsilon\:}_{\infty\:}\), \(\:e\) and \(\:N\) denote the velocity of light, effective electron mass, vacuum permittivity, high-frequency dielectric constant, electron charge and carrier concentration, respectively. For ITO, \(\:{m}^{*}\) = 0.3\(\:{m}_{0}\), \(\:{\epsilon\:}_{\infty\:}\) = 3.8 and \(\:{m}_{0}\) is the free-electron mass61. Based on Hall measurements, the carrier concentrations of the ITO films deposited at oxygen partial pressures of 0 and 0.011 are 15.7 × 1020 cm− 3 and 4.7 × 1020 cm− 3, respectively. Using these values in Eq. (1), the corresponding plasma wavelengths are calculated to be approximately 912 nm and 1667 nm (Figure S3). These results support the observed trend that a lower carrier concentration results in a longer plasma wavelength, leading to an increase in the transmission region. Therefore, ITO with lower carrier concentration (higher oxygen partial pressure, 0.011) exhibits higher transmittance in the SWIR range. Based on these results, the oxygen partial pressure for the top gate ITO was set to 0.011 to maximize SWIR transmittance.

Structural analysis of channel materials and device

Figure 2a shows a cross-sectional TEM image of a dual-gate Te/Se phototransistor, illustrating the overall vertically stacked device structure. The image clearly reveals the key components, including the buried bottom gate (Ni), bottom gate dielectric layers (Al2O3/SiO2), channel layer (Te/Se alloy), passivation and top gate dielectric (Al2O3) and top gate (ITO). Figure 2b show electron energy dispersive X-ray spectroscopy (EDS) mapping images showing the elemental distribution within the device. These images clearly show the presence of the device components and demonstrate the uniform distribution of Te and Se elements within the channel layer. The crystal structure of the Te/Se alloy thin film was investigated using HR-TEM and HR-STEM. As shown in Fig. 2c, the stacking of the bottom gate dielectric, channel layer, passivation layer and top gate dielectric is clearly identified. Additionally, the deposited Te/Se alloy thin film exhibits a thickness of approximately 10 nm. In the HR-STEM image of Fig. 2d, a hexagonal crystal structure is distinctly observed. The (110) and (003) planes were also identified, with interplanar spacing of 0.197 and 0.386 nm, respectively. These interplanar spacing are smaller than those of Te crystals, which are 0.209 and 0.398 nm, respectively62. This is due to the partial substitution of Se atoms (0.14 nm), which have a smaller atomic radius than Te atoms (0.16 nm)50. Furthermore, the fast Fourier transform (FFT) pattern (Fig. 2e) exhibits distinct and well-arranged diffraction spots, confirming the high crystallinity of the Te/Se alloy thin film.

Fig. 1
figure 1

(a) Schematic illustration of the Te/Se alloy based dual-gate phototransistor device structure. (b) Crystal structure schematic of the Te/Se alloy. (c) Optical image of a fabricated dual-gate phototransistor based on a Te/Se alloy thin film. (d) Comparison of operating mechanisms between a single gate and a dual-gate phototransistor, demonstrating enhanced charge separation under SWIR illumination in the dual-gate device. (e) SWIR transmittance of top gate ITO at an oxygen partial pressure of (O2 / O2 + Ar) 0.011 during ITO deposition.

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Fig. 2
figure 2

Overall device structure and crystal structure analysis of Te/Se. (a) Cross-sectional TEM image of a dual-gate Te/Se phototransistor. (b) EDS mapping images of elemental distribution. (c) HR-TEM image showing the bottom gate, channel layer, and passivation layer. (d) HR-STEM image of a Te/Se alloy. The red circles represent Te/Se atoms. (e) FFT pattern of Te/Se alloy.

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Fig. 3
figure 3

Material characteristics of Te and Te/Se alloy. (a) Raman spectra of Te and Te/Se alloy thin films. The inset show schematic vibration patterns of the Raman modes of E1, A1 and E2 (b) XRD pattern of Te and Te/Se alloy thin films. (c) AFM image of Te/Se alloy thin film, Ra represents the arithmetic mean deviation of surface roughness. (d) Absorbance spectrum of the Te and Te/Se alloy thin film. The inset show Tauc plot of absorbance spectrum (e) XPS spectra of Te and Te/Se thin films, including their respective Al2O3 passivation layers.

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Fig. 4
figure 4

Electrical characteristics of Te0.7Se0.3 TFT with and without both Al2O3 passivation and SiO2 interfacial layer. (a) Schematic illustration of the Te0.7Se0.3 TFT device structure. (b) Optical image of a fabricated Te0.7Se0.3 TFT. (c) Schematic illustration for carriers transport in with and without a SiO2 interfacial layer. (d, e) Transfer and output characteristics of Te0.7Se0.3 TFTs with and without both passivation and SiO2 interfacial layer. (f, g) Electrical parameter comparison of the Te0.7Se0.3 TFTs with and without both passivation and the SiO2 interfacial layer. (h) Threshold voltage shift (∆VTH) of the Te0.7Se0.3 TFTs with and without a SiO2 interfacial layer under PBS test measured at stress condition of 9.1 and 6.7 V, respectively.

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Fig. 5
figure 5

Electrical characteristics of dual-gate Te0.7Se0.3 TFT. (a, b) Transfer and output characteristics of dual-gate Te0.7Se0.3 TFT. The inset in (a) shows an optical image of a fabricated device. (c) Extracted values of mobility (µFE) and subthreshold slope (SS) in TG, BG and DG mode. (d) Transfer characteristics of dual-gate Te0.7Se0.3 TFTs with varying VTG from − 2 to 6 V in steps of 2 V. (e) Contour plot of drain current as a function of VBG and VTG, extracted from (d).

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Fig. 6
figure 6

Photoresponse characteristic of dual-gate Te0.7Se0.3 phototransistor. (a) Transfer characteristics of dual-gate Te0.7Se0.3 phototransistor with varying VTG from − 2 to 6 V in steps of 2 V under 1050 nm illumination. (b) Extracted values of responsivity (R) and specific detectivity (D*) as a function of VTG. (c) Time-resolved photoresponse of the dual-gate Te0.7Se0.3 phototransistor, measured for different VTG. Explanatory band diagrams of (d) single-gate phototransistor, (e) dual-gate phototransistor with oppositely biased VBG and VTG and (f) dual-gate phototransistor under SWIR illumination. Extracted values of (g) responsivity and (h) specific detectivity as a function of illumination power under 1050, 1200 and 1300 nm illumination.

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Optical and surface analysis of Te and Te/Se alloy thin films

Figure 3a shows the Raman spectra of Te and Te/Se alloy thin films. The Raman spectra of Te thin films exhibits three vibration modes at approximately 100, 125 and 142 cm− 1, corresponding to the E1, A2 and E2 peaks, which are consistent with previous literature reports63,64. The A1 mode is induced by the stretching caused by the motion of each atom in the helical chain and the two E modes are induced by the asymmetric stretching of the helical chain along the c-axis65. Upon partial substitution of Te atoms with Se atoms, the A1 and E2 modes shift to larger wavenumbers and turn into broad peaks. The crystal structures of Te and Te/Se alloy thin films were investigated using X-ray diffraction (XRD), as shown in Fig. 3b. The diffraction patterns closely match the hexagonal crystal structure of Te (JCPDS 36-1452). Upon Se was alloyed all diffraction peaks shift slightly toward higher angles, indicating a reduction in the lattice constant50. This shift can be attributed to the partial substitution of Te atoms (0.16 nm) with smaller Se atoms (0.14 nm)50, as illustrated in Fig. 2d. The surface morphology of the Te/Se alloy thin films was investigated by atomic force microscopy (AFM) in a scanning area of 1.5 × 1.5 μm. As shown in Fig. 3c, the Te/Se alloy thin film exhibits smooth and uniform surface with an arithmetic-mean deviation roughness (Ra) of 0.82 nm. Additionally, the absorbance of Te and Te/Se alloy thin films on soda-lime glass are shown in Fig. 3d. The absorbance was calculated using the following Eq.

$$\:\text{Ab}\text{sorbance\:}\left(\text{\%}\right)\text{=\:100\:\--\:Reflectance\:}\left(\text{\%}\right)\text{\:\--\:Transmittance\:(\%)}$$
(2)

The absorbance of the Te/Se alloy thin film is 38% in the visible range (550 nm) and 17% in the SWIR range (1050 nm). The reflectance and transmittance are shown in Figure S4, respectively. The inset in Fig. 3d shows the optical bandgap of Te and Te/Se alloy thin film extracted from the absorbance spectra using Tauc plot method66. The bandgap value (1.05 eV) of the Te/Se alloy thin film is 0.13 eV larger than that of the Te thin film (0.92 eV), which can be attributed to the inherently wide bandgap of Se (1.8 eV). The absorbance in the SWIR is overall higher for Te thin films than for Te/Se alloy thin films. However, in terms of fundamental transistor characteristics, which should have a low off-state current (Ioff), Te/Se alloy thin films have an advantage. This will be discussed in the following section.

The elemental composition and chemical state of the Te and Te/Se thin films, along with their respective passivation layers (Al2O3), were investigated by X-ray photoelectron spectroscopy (XPS). As shown in Fig. 3e, the Te 3d XPS spectrum exhibits two distinct peaks at 572.8 and 583.2 eV, corresponding to Te0 3d5/2, Te0 3d3/2 bonds, respectively. In addition, two XPS peaks located at 576.0 and 586.4 eV correspond to Te4+ 3d5/2, Te4+ 3d3/2 bonds, respectively, indicating the oxidation state of Te67,68. Notably, no detectable Te4+ peaks were observed in Te and Te/Se alloy thin films after Al2O3 passivation. The detailed deconvoluted Te0 3d5/2 peaks are shown in Figure S5. This is well known to be the reduction of Te thin films due to the deposition of the Al2O3 passivation layer using a trimethylaluminum(TMA) precursor during atomic layer deposition (ALD)38,63. In addition, in the Te/Se alloy, the binding energy increases due to the higher electronegativity of Se (2.55) compared to Te (2.1). The stronger electron-attracting ability of Se shifts the electron density toward Se atoms, reducing the electron density around Te50. This reduction in electron density enhances the electrostatic attraction between the Te nucleus and its remaining electrons, leading to an increase in binding energy. The depth profiles of the atomic composition in Te thin films and Te/Se alloy thin films are shown in Figure S6. The depth profiles indicate the presence of Te and Te/Se layers up to a depth of approximately 10 nm, confirming a Te/Se composition ratio of 7:3.

Electrical behavior in bottom single gate structure depending on SiO2 interfacial layer

Figure 4a and b show the schematic device structure and optical image of Te0.7Se0.3 TFT with a single bottom gate configuration, respectively. The dimension of fabricated device has a channel length (L) of 2 μm and a width (W) of 3 μm. As illustrated in the schematic in Fig. 4c, carrier scattering and charge trapping induced by defects within Al2O3, a high-k gate dielectric, significantly degrade hole mobility in the channel due to its high interface trap density and intrinsic material defects. The relatively weak Al–O bonds in Al2O3, characteristic of high-k dielectrics, lead to a high density of oxygen vacancies and structural disorder, which act as charge trapping center69. To mitigate these effects, a 5 nm SiO2 interfacial layer was introduced, as its strong Si–O bonds and low defect density provide chemical stability, reducing interface defect states and suppressing charge trapping69,70,71. The effect of this insertion on device performance will be discussed in the following section. The transfer characteristics of the Te0.7Se0.3 TFTs are obtained by sweeping bottom gate voltage from 8 to -8 V at a drain voltage of -1 V (Fig. 4d). The Te0.7Se0.3 TFT exhibits a progressive improvement in electrical performance with the introduction of Al2O3 top passivation and SiO2 bottom interfacial layer. Figure 4e shows the output characteristics obtained by sweeping drain voltage from 0 to -5 V, while bottom gate voltage from − 8 V in 2 V increments. The device exhibits clear ohmic contact property and pinch-off behavior. A significant improvement in device performance compared to Te-based TFT is observed, as detailed in Figure S7. Furthermore, the effects of Al2O3 passivation and the presence of the SiO2 interfacial layer on device characteristics are presented in Fig. 4f and g. The hysteresis of Te0.7Se0.3 TFTs decreased from 7.8 to 1.8 V with the introduction of both passivation and a SiO2 interfacial layer. Additionally, the field-effect mobility (\(\:\upmu\text{FE}\)) increased from 0.2 to 2.3 cm2V− 1s− 1. The interface trap density (\(\:{\text{D}}_{\text{it}}\)) was reduced from 7.9 × 1013 to 3.3 × 1013 cm− 2eV− 1, while the subthreshold slope (\(\:\text{SS}\)) improved from 3.1 to 1.8 V/dec. The values of \(\:\upmu\text{FE}\), \(\:{\text{D}}_{\text{it}}\) and \(\:\text{SS}\) were calculated using the following equation63.

$$\:\upmu\text{FE\:}\text{=\:}\frac{\text{L}{\text{\:g}}_{\text{m,max}}}{\text{W}{\text{}\text{C}}_{\text{OX}}{\text{}\text{V}}_{\text{D}}}$$
(3)
$$\:{\text{D}}_{\text{it}}\text{\:=\:}\left[\frac{\text{qSS\:}{\text{log}}_{\left(\text{e}\right)}}{\left(\text{k}\text{T}\right)}-1\right]\frac{{\text{C}}_{\text{OX}}}{\text{q}}$$
(4)
$$\:\text{SS\:}\text{=}{\:\left(\frac{\text{d}\left(\text{log}{\text{I}}_{\text{D}}\right)}{\text{d}\left({\text{V}}_{\text{G}}\right)}\right)}^{\text{-1}}$$
(5)

Here, \(\:{\text{\:g}}_{\text{m,max}}\), \(\:{\text{C}}_{\text{OX}}\),\(\:{\text{}\text{V}}_{\text{D}}\), \(\:{\text{I}}_{\text{D}}\), \(\:{\text{V}}_{\text{G}}\), \(\:\text{k}\), \(\:\text{q}\) and \(\:\text{T}\:\)denote the maximum transconductance, gate oxide capacitance, drain voltage, drain current, gate voltage, Boltzmann constant, electron charge and absolute temperature, respectively. In addition, the hysteresis was determined as the difference in \(\:{V}_{\text{T}\text{H}}\) between forward and backward sweeps, extracted using linear extrapolation (Figure S8)72. The difference in electrical properties with and without Al2O3 passivation is attributed to the reduction of oxygen-induced defects38,72, which occur due to the oxidation of Te and Te0.7Se0.3 thin films, as confirmed by the XPS results. To experimentally prove the contribution of the SiO2 interfacial layer, the electrical stability test under positive bias stress (PBS) was performed for 2000 s. Figure S9 shows the change in drain current of transfer characteristics under PBS test for devices with and without the SiO2 interfacial layer. The initial values for \(\:{V}_{\text{T}\text{H}}\) for the devices with and without SiO2 are − 1.1 and 1.3 V, respectively. Since the PBS test must consider the same gate overdrive (\(\:{V}_{\text{G}}\)-\(\:{V}_{\text{T}\text{H}}\)), \(\:{V}_{\text{G}}\) = 9.1 and 6.7 V were applied to the devices with and without SiO2, respectively73. As shown in Fig. 4h, the device with the SiO2 interfacial layer exhibits a lower threshold voltage shift (\(\:{{\Delta\:}V}_{\text{T}\text{H}}\)) with increasing stress time in the PBS test, showing a shift of -1.48 V compared to -3.68 V for the device without SiO2 interfacial layer. The \(\:{{\Delta\:}V}_{\text{T}\text{H}}\) typically influenced by the amount of trapped charge near the interface between the channel region and the gate dielectric44. Furthermore, as shown in Fig. 4g, the \(\:{\text{D}}_{\text{it}}\text{}\) values for the devices with and without the SiO2 interfacial layer are 3.3 × 1013 and 5.3 × 1013 cm[− [2eV[− [1, respectively. Therefore, we experimentally demonstrate that the SiO2 interfacial layer effectively reduces carrier scattering induced by defects in Al2O3.

Electrical behavior of dual-gate Te0.7Se0.3 TFT

First, TG and BG mode mean that the gate voltage is applied to the top and bottom gate, respectively. DG mode means that the bottom gate and top gate are biased simultaneously and can control the channel together. Figure 5a shows the transfer characteristics (drain current versus gate voltage) of dual-gate Te0.7Se0.3 TFT single device with three different operation modes of TG, BG and DG, respectively. The optical image of device is also shown in the inset of Fig. 5a. The sweep range of gate voltage are from 8 to -8 V with fixed drain voltage of -1 V. Notably, the electrical performance of BG mode is slightly enhanced compared with that of TG mode, exhibiting that on-current increased while the off-current decreased. The difference in electrical properties results between the BG and TG mode could be explained in terms of interface property from the change in gate dielectric, where the bottom gate dielectric is composed of Al2O3/SiO2, while the top gate dielectric is composed of Al2O3 only. The reason why the top gate dielectric is composed only of Al2O3 is attributed to the direct reducing effect of Al2O3 on Te and Te0.7Se0.3 thin films. More interestingly, the DG mode significantly exhibit enhanced device performance owing to the enhanced gate controllability on the channel. The improved performance in DG mode is attributed to the rapid reach of the Fermi level (EF) to the conduction band edge (ECB)70. Thus, the device performances with subthreshold swing (\(\:\text{SS}\)), on-current, and off-current are simultaneously enhanced as shown in Fig. 5a. Figure 5b shows the output characteristics (drain current versus drain voltage) of dual-gate Te0.7Se0.3 TFT with three different operation modes of TG, BG and DG, respectively. The DG mode shows the most superior electrical characteristics in three different operation modes. In particular, the saturation behavior of drain current occurs earlier with the drain voltage of around − 2 V, which is due to the enhanced gate controllability in the DG mode. The important device parameters of the field-effect mobility (\(\:\upmu\text{FE}\)) and subthreshold swing (\(\:\text{SS}\)) are plotted as shown in Fig. 5c. The \(\:\text{SS}\), Ion/off and \(\:\upmu\text{FE}\) for TG mode are 3.2 V/dec., 2.4 × 103 and 0.4 cm2V− 1s[− [1, respectively, while for BG mode are 2.8 V/ dec., 2.8 × 104 and 0.9 cm2V− 1s[− [1. Meanwhile, the DG mode exhibit enhanced device performance with 1.9 V/dec., 1.3 × 105 and 3.8 cm2V− 1s[− [1 (Fig. 5a-c).

In Fig. 5d, the transfer characteristic was measured by sweeping the bottom gate voltage (\(\:{V}_{\text{B}\text{G}}\)) from 8 to -8 V while applying the top gate voltage (\(\:{V}_{\text{T}\text{G}}\)) from − 2 to 6 V in steps of 2 V and \(\:{V}_{D}\) = -5 V. As \(\:{V}_{\text{T}\text{G}}\) increases from − 2 to 6 V, the threshold voltage shifts to a more negative value and the drain current decreases. The linear-scale transfer characteristics of the device for the extraction of threshold voltages with different \(\:{V}_{\text{T}\text{G}}\) is shown in Figure S10. A positive \(\:{V}_{\text{T}\text{G}}\) depletes the p-channel accumulated by the bottom gate in the semiconductor layer, leading to a decrease in the threshold voltage by effectively reducing the hole density in the channel59. Additionally, the decrease in drain current at a positive \(\:{V}_{\text{T}\text{G}}\) is attributed to electron accumulation at the top dielectric interface, which induces the formation of two conductive channels, n-type and p-type. This dual-channel effect facilitates more efficient separation of photogenerated electron-hole pairs by creating a built-in field. In summary, the changes in drain currents with respect to bias polarity between bottom and top gate voltage is shown as a contour plot in Fig. 5e.

SWIR photodetection performance and operation mechanism

Figure S11 shows a comparison of the transfer characteristics for devices using ITO and Ni as the top gate material. In both cases, the transfer characteristics are similar, indicating that the influence of the top gate material on device performance is not significant. However, under 1050 nm light illumination, only ITO allows light transmission, leading to a clear photoresponse in the device with an ITO top gate (Figure S11). To investigate the optical properties of DG Te0.7Se0.3 phototransistors with an ITO top gate, we measured the transfer characteristics under 1050 nm light illumination by sweeping \(\:{V}_{\text{B}\text{G}}\) while applying \(\:{V}_{\text{T}\text{G}}\) from − 2 to 6 V in steps of 2 V and \(\:{V}_{\text{D}}\) = -5 V. As shown in Fig. 6a, the amounts of relative photocurrent changes between dark and illumination states increase noticeably when 1050 nm light is illuminated under oppositely biased \(\:{V}_{\text{T}\text{G}}\:\)and \(\:{V}_{\text{B}\text{G}}\). To quantitatively compare the photoelectric properties at different \(\:{V}_{\text{T}\text{G}}\) values at fixed \(\:{V}_{\text{B}\text{G}}\) = -8 V, the responsivity (\(\:\text{R}\)) and specific detectivity (\(\:{\text{D}}^{\text{*}}\)) are extracted from Fig. 6a and shown in Fig. 6b. \(\:\text{R}\) and \(\:{\text{D}}^{\text{*}}\) are calculated by the following Eqs. 17.

$$\:\text{R}=\frac{{I}_{ph}}{{P}_{in}\times\:A}$$
(6)
$$\:{D}^{*}=R\sqrt{A/2e{I}_{dark}}$$
(7)

Here, \(\:{I}_{ph}\), \(\:{P}_{in}\) and \(\:A\) denote the photocurrent, illumination power density and active area, respectively. As \(\:{V}_{\text{T}\text{G}}\) increases from − 2 to 6 V, the R of the phototransistor increased from 106.1 A/W to 646.1 A/W while \(\:{\text{D}}^{\text{*}}\) increased from 1.81 × 1010 Jones to 2.24 × 1011 Jones. To further characterize the photo-switching behavior at varying \(\:{V}_{\text{T}\text{G}}\), the time-resolved photocurrent is shown in Fig. 6c. Measurements were performed under varying \(\:{V}_{\text{T}\text{G}}\), ranging from 6 to -2 V in 2 V steps with \(\:{V}_{\text{D}}\) = -5 V under 1050 nm light illumination. The illumination was switched to ON and OFF states at intervals of 20 s, respectively. Under conditions where \(\:{V}_{\text{B}\text{G}}\) and \(\:{V}_{\text{T}\text{G}}\) are oppositely biased, an increase in \(\:{V}_{\text{T}\text{G}}\:\)leads in an enhanced photocurrent gain. Furthermore, the relatively weak persistent photoconductance (PPC) effect indicates that charge trapping is suppressed by the SiO2 interfacial layer. In addition to these results, we measured the low-frequency noise (1–10 Hz) of the devices under \(\:{V}_{\text{D}}\) = -5 V, \(\:{V}_{\text{B}\text{G}}\) = -8 V and \(\:{V}_{\text{T}\text{G}}\) = 0 (single-gate) or 6 V (dual-gate). Figure S12 (a) shows that the extracted current noise spectral densities were 9.22 × 10−22 A2/Hz and 7.31 × 10− 22 A2/Hz for single-gate and dual-gate operation, respectively. Using these measured noise values, we evaluated the specific detectivity according to

$$\:{D}^{*}=\frac{R\sqrt{A}}{\sqrt{S\varDelta\:f}}$$
(8)

.

The noise-based \(\:{\text{D}}^{\text{*}}\) values are 1.33 × 109 Jones for single-gate and 5.85 × 109 Jones for dual-gate operation as shown in Figure S12 (b). Although these noise-based \(\:{\text{D}}^{\text{*}}\) values are lower than those previously calculated in Eq. (7), the dual-gate device consistently maintains a substantially higher \(\:{\text{D}}^{\text{*}}\) than its single-gate counterpart, confirming the performance advantage of the dual-gate configuration even when noise is considered.

Figures 6d and e illustrate simplified band diagrams of the single bottom-gate and dual-gate phototransistors, respectively, while Fig. 6f presents the band diagram of the dual-gate phototransistor under SWIR illumination. In the single-gate phototransistor, when a bias of \(\:{V}_{\text{B}\text{G}}\) < 0 V is applied with \(\:{V}_{\text{T}\text{G}}\) = 0 V, the holes accumulate at the bottom interface, leading to upward band bending in the channel region. In the dual-gate phototransistor, when a bias of \(\:{V}_{\text{B}\text{G}}\) < 0 V is applied with \(\:{V}_{\text{T}\text{G}}\) > 0 V, the band structure at the bottom interface bends upward, similar to the single-gate configuration. Simultaneously, a positive top-gate bias (\(\:{V}_{\text{T}\text{G}}\) > 0 V) induces electron accumulation at the top interface, resulting in downward band bending. Consequently, under oppositely biased \(\:{V}_{\text{T}\text{G}}\) and \(\:{V}_{\text{B}\text{G}}\), separated n-type and p-type channels are formed, leading to the establishment of a built-in field. Upon SWIR illumination, photogenerated electron–hole pairs are effectively separated and transported by this built-in field, resulting in an enhanced photocurrent.

A clear photoresponse is observed under illumination at 1050, 1200 and 1300 nm wavelengths (Figure S13). Photocurrent is also clearly shown in the transfer characteristics even when \(\:{P}_{in}\) is below 1 mW/cm2. Figure 6g and f show the photo responsivity (\(\:\text{R}\)) and specific detectivity (\(\:{\text{D}}^{\text{*}}\)) as a function of illumination power extracted from the transfer characteristic in Figure S14. At a the top gate voltage of 6 V and varying illumination power (1–14 mW/cm2) at 1050 nm, the phototransistor exhibited a responsivity from 2607.7 to 432.5 A/W and a specific detectivity from 9.03 × 1011 to 1.15 × 1011 Jones. As the illumination power increases, responsivity and specific detectivity decrease, which is attributed to the enhanced recombination activity of photo-generated carriers75. Under illumination at 1200 nm, with power densities of 0.5 to 5 mW/cm2, the responsivity ranged from 685.7 to 159.1 A/W, while the specific detectivity ranged from 2.21 × 1011 to 5.13 × 1010 Jones. Furthermore, at 1300 nm, with illumination power densities between 0.5 and 8 mW/cm2, the device exhibited a responsivity of 559.3 to 142.6 A/W and a specific detectivity of 1.91 × 1011 to 4.86 × 1010 Jones. To compare the performance of Te0.7Se0.3 dual-gate phototransistors, we compare the performance of tellurium-based phototransistors as summarized in Table 1. The comparison categorizes the devices based on their material, on/off current ratio, mobility, responsivity and detectivity. Compared to previously reported phototransistors, the dual-gate Te0.7Se0.3 device showed high \(\:\text{R}\), \(\:{\text{D}}^{\text{*}}\) in SWIR due to the separation of electron-hole pairs in the dual-gate.

Table 1 Performance comparison of tellurium-based phototransistor.
Full size table

Conclusions

In summary, we successfully fabricated a dual-gate phototransistor based on high crystalline quality Te0.7Se0.3 alloy thin film, demonstrating excellent electrical and optoelectronic properties. To further optimize the device, we introduced SiO2 interfacial layer to reduce carrier scattering at the channel/gate dielectric interface and Al2O3 passivation to reduce oxygen defects in the Te0.7Se0.3 alloy thin film and tuned the oxygen partial pressure of ITO to enhance SWIR light transmission. As a result, the Te0.7Se0.3 dual-gate phototransistor exhibited \(\:\upmu\text{FE}\) of 3.8 cm2V− 1s− 1 and \(\:\text{SS}\) of 1.9 V/dec. Additionally, the selective control of the top and bottom gates induced a built-in field, effectively collecting photogenerated electrons and holes to achieve high responsivity. The device demonstrated a responsivity of 559.3 A/W under 1300 nm light illumination. The Te0.7Se0.3 alloy thin film-based dual-gate architecture provides a promising strategy for achieving high-performance, cost-effective SWIR photodetectors, paving the way for advanced optoelectronic applications.