Advanced Transistor Technologies for Nanoscale CMOS Devices

The relentless drive towards finer process nodes has transformed complementary metal-oxide-semiconductor (CMOS) technology from two-dimensional planar transistors into sophisticated three-dimensional architectures. By introducing multiple gate electrodes in fin field-effect transistors (FinFETs) and encapsulating the channel in gate-all-around FETs (GAAFETs), device engineers have gained superior electrostatic control and mitigated short-channel effects. Beyond the current 3-nm generation, stacking transistors vertically in complementary FETs (CFETs) and employing nanosheet or nanowire channels are emerging as critical strategies to boost integration density while preserving performance and power efficiency. Innovative contact engineering and inner-spacer formation have further reduced parasitic resistance and capacitance, enabling robust drive currents at sub-20-nm gate lengths. Concurrent exploration of alternative channel materials, such as III–V semiconductors and two-dimensional materials, promises enhanced carrier mobility and novel device functionalities. These advances underpin next-generation applications ranging from ultra-low-power Internet of Things nodes to high-performance computing, ensuring the continued relevance of Moore’s Law in an era of quantum and thermal limitations.

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Advanced Transistor Technologies for Nanoscale CMOS Devices publication trend

The graph below shows the total number of articles in advanced transistor technologies for nanoscale cmos devices across all publications each year (not limited to Nature Index journals).

Technical terms

Complementary metal-oxide-semiconductor (CMOS): A mainstream technology for digital logic in which n-type and p-type transistors are paired to minimise static power dissipation.

Fin field-effect transistor (FinFET): A three-dimensional transistor in which a thin fin-shaped channel protrudes from the substrate, wrapped by a gate on multiple sides to improve electrostatic control.

Gate-all-around FET (GAAFET): A transistor in which the gate electrode completely surrounds the channel, often realised as stacked nanosheets or nanowires, offering optimal gate control and reduced short-channel effects.

Complementary FET (CFET): A device architecture featuring vertically stacked n-type and p-type transistors sharing a common gate, aimed at maximising circuit density and reducing interconnect length.

Short-channel effects: Undesirable phenomena, including threshold voltage roll-off and drain-induced barrier lowering, that occur when transistor channel lengths approach the nanometre scale.

References

1. New structure transistors for advanced technology node CMOS ICs. National Science Review (2024).
2. Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering. Nano Letters (2024).
3. Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes. IEEE Access (2020).
4. Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors. Nanomaterials (2020).
5. Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET. IEEE Journal of the Electron Devices Society (2021).