Digital Electronic Devices

Digital electronic devices encompass a broad spectrum of semiconductor‐based components and circuits that process, store and transmit binary information. At the fundamental level lie field‐effect transistors (FETs), which form logic gates, memory cells and analogue interfaces. Thin‐film transistors deposited on glass, plastic or silicon substrates enable large‐area displays, flexible sensors and back‐end‐of‐line integration of memory and logic. Three‐dimensional (3D) NAND flash memory overcomes planar scaling limits by stacking hundreds of charge‐trap layers vertically, supporting multi‐level storage and ultrahigh areal densities. Charge‐trap nitride architectures, multi‐level cells and advanced programme/erase algorithms address endurance, retention and intercell interference in solid‐state drives. Device ageing phenomena—such as bias temperature instability in MOSFETs—drive the development of predictive reliability models and defect‐engineering strategies. Machine‐learning‐guided optimisation of trap distributions and defect profiles within dielectrics and channel materials is emerging as a means to accelerate performance–reliability trade‐offs. Across the digital ecosystem, innovations in material synthesis, nanoscale patterning and circuit architectures underlie the transition to ever more energy‐efficient, high‐speed and non‐volatile electronics for applications ranging from consumer displays and the Internet of Things to data‐centre storage and cryogenic computing.

Research from Nature Portfolio

A universal multi-project-wafer platform has been demonstrated for two mainstream flexible TFT technologies—amorphous indium–gallium–zinc oxide and low-temperature polycrystalline silicon—validating a fabless ecosystem by implementing a classical 6502 microprocessor design in both materials. This work establishes foundry models for large-area flexible logic and paves the way for scalable, heterogeneous integration of TFT‐based systems.

High-mobility, hydrogenated polycrystalline indium oxide channels, fabricated by low-temperature solid-phase crystallisation, achieve field‐effect mobilities above 130 cm² V⁻¹ s⁻¹, subthreshold swings below 0.2 V/decade and low threshold voltages. These transparent, flexible TFTs require no exotic equipment and promise monolithic integration of display, sensing and memory functions.

Atomic-layer-deposited zinc oxide TFTs with record field-effect and intrinsic mobilities (85/140 cm² V⁻¹ s⁻¹) have been co‐integrated with resistive memory elements in back-end-of-line circuits. This demonstration of CMOS-compatible, 3D memory‐logic arrays underscores the potential of ALD dielectrics for high‐density, low-temperature process flows in next-generation integrated electronics.

Research from all publishers

A holistic machine-learning framework has been applied to the design of spatial and energetic trap distributions in the silicon-nitride layer of 3D NAND flash. By training neural networks on extensive TCAD‐generated data, optimal trap profiles were identified that balance programme/erase speed with data retention and cycling endurance, offering rapid guidelines for future charge-trap architectures.

A comprehensive review of 3D NAND flash architectures and process integration traces the evolution from 24 to over 170 vertical layers, detailing wafer bonding, deep channel etching and CMOS-under-array innovations. The article outlines scaling to triple- and quad-level cells, penta-level schemes and advanced algorithmic controls for short-term retention and large-block throughput.

A state-of-the-art survey of bias temperature instability in MOSFETs synthesises physical mechanisms underlying NBTI and PBTI, reviews advanced measurement techniques to separate defect contributions and presents predictive models spanning DC, AC and cryogenic regimes. This work guides material and bias-scheme engineering to mitigate threshold‐voltage shifts over device lifetimes.

Digital Electronic Devices publication trend

The graph below shows the total number of articles in digital electronic devices across all publications each year (not limited to Nature Index journals).

Technical terms

Thin-film transistor (TFT): A field-effect device in which the semiconductor channel is deposited as a thin film on a substrate, enabling large-area and flexible electronics.

Back-end-of-line (BEOL): The process stages after transistor formation, involving interconnects, dielectrics and passive components, typically constrained to low temperatures below metal-interconnect budgets.

Field-effect mobility: The carrier drift velocity per unit electric field in a transistor channel, determining drive current and switching speed.

3D NAND: A non-volatile memory architecture that stacks multiple layers of charge-trap or floating-gate cells vertically to extend areal density beyond planar limits.

Charge-trap nitride (CTN): A dielectric layer that stores charge in defect sites rather than a conductive floating gate, simplifying fabrication and enhancing endurance in 3D NAND cells.

Multi-level cell (MLC): A memory cell that encodes more than one bit by using multiple threshold-voltage states, including triple-level (TLC), quad-level (QLC) and penta-level schemes.

Threshold voltage (Vth): The gate voltage at which a transistor channel begins to conduct, critical for read/write margins in logic and memory applications.

Bias temperature instability (BTI): A reliability phenomenon in MOSFETs where prolonged gate stress at elevated temperature leads to threshold-voltage shifts due to defect generation and charge trapping.

Technology computer-aided design (TCAD): A suite of physics-based simulation tools for modelling semiconductor devices and process integration, enabling virtual prototyping of electrical behaviour.

References

1. Multi-project wafers for flexible thin-film electronics by independent foundries. Nature (2024).
2. High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors. Nature Communications (2022).
3. CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor. Nature Communications (2023).
4. Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning. IEEE Access (2023).
5. Architecture and Process Integration Overview of 3D NAND Flash Technologies. Applied Sciences (2021).
6. Bias Temperature Instability of MOSFETs: Physical Processes, Models, and Prediction. Electronics (2022).