Current-Steering Digital-to-Analog Converter Techniques

Current-steering digital-to-analog converters (CS-DACs) form the backbone of high-speed mixed-signal systems, combining fast settling times with wide bandwidth and high dynamic range. These architectures employ arrays of matched current sources that direct analogue output currents through precision switches according to the digital input code. Key challenges include minimising mismatch-induced distortion, controlling spurious content, and maintaining linearity across wide frequency ranges. Techniques such as dynamic element matching (DEM), segmentation and unary-weighted layouts serve to randomise or calibrate element errors. Output-impedance matching and compensation methods address distortion from finite source resistance, while advanced switching schemes mitigate output-dependent modulation (ODM). Emerging approaches exploit optimal element-arrangement algorithms to correct static nonlinearity, and novel isolation strategies in differential-quad structures suppress mid-to-high-frequency spurs. Together, these innovations enable CS-DACs to achieve high spurious-free dynamic range (SFDR), low energy per conversion, and suitability for applications from continuous-time ADCs to radio-frequency waveform generation.

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A tri-level CS-DAC design has demonstrated 12-bit static linearity combined with improved impedance matching suitable for continuous-time ADCs. By analysing mismatch, noise and output-impedance distortion, a three-level switching scheme and a novel compensation technique yielded an ~8 dB enhancement in dynamic performance across the Nyquist band at 100 MS/s in a 65 nm CMOS implementation.

A study addressing output-dependent modulation in a differential-quad CS-DAC introduced isolation devices to suppress two categories of ODM errors: output transition and boundary-effect errors. Simulations and measurement on a 16-bit, 250 MS/s DAC in 180 nm CMOS showed a 13 dB reduction in odd-harmonic spurs, affirming the efficacy of the isolation approach for high-resolution, mid-to-high-frequency operation.

An analytical framework for energy consumption bounds in CMOS CS-DACs correlated signal-to-noise ratio (SNR) and SFDR requirements to minimum energy per conversion. Deriving noise, speed and linearity design corners revealed that scaling down device dimensions shifts the dominant constraint to noise bound beyond an estimated SNR of 40 dB in 65 nm technology. These results offer a reference for designers seeking to minimise energy in wideband, high-precision CS-DACs.

Current-Steering Digital-to-Analog Converter Techniques publication trend

The graph below shows the total number of articles in current-steering digital-to-analog converter techniques across all publications each year (not limited to Nature Index journals).

Technical terms

Current-steering DAC: A converter architecture using matched current sources and binary-weighted switching to produce analogue outputs according to digital codes.

Spurious-Free Dynamic Range (SFDR): The ratio between the amplitude of the fundamental signal and the largest spurious spectral component, indicating spectral purity.

Dynamic Element Matching (DEM): A randomisation or calibration technique that rotates or shuffles unit elements to average out static mismatches and reduce spurious distortion.

Output-Dependent Modulation (ODM): Nonlinear distortion arising from interactions between switching transitions and output loading, often categorised into transition-error and boundary-effect components.

Impedance matching: The process of adjusting source and load resistances to minimise reflections and distortion due to finite output impedance of current-steering elements.

References

1. Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs. IEEE Open Journal of Circuits and Systems (2020).
2. Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters. Analog Integrated Circuits and Signal Processing (2022).
3. Modeling and Mitigating Output-Dependent Modulation in Current-Steering DAC Based on Differential-Quad Switching Scheme. Electronics (2024).
4. Static-Linearity Enhancement Techniques for Digital-to-Analog Converters Exploiting Optimal Arrangements of Unit Elements. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2024).