Graphene-Based Field-Effect Transistors and Heterostructure Electronics

Graphene, a monolayer of sp²-hybridised carbon atoms, offers exceptional carrier mobility and mechanical flexibility, making it an ideal candidate for next-generation electronics. Field-effect transistors (FETs) built on graphene exploit its two-dimensional nature to achieve high on-off ratios, low power consumption and ultrafast switching. When graphene is combined with other two-dimensional semiconductors or insulators through weak van der Waals forces, heterostructure devices emerge that can be tailored at the atomic scale. Such stacked architectures enable vertical transport channels, tunable band alignments and novel barrier modulation schemes. Recent advances have addressed key challenges in downscaling, subthreshold steepness and environmental robustness, paving the way for ultra-dense logic circuits, ambipolar photodetectors and temperature-invariant switches. The convergence of FET design and heterostructure engineering promises transformative improvements in energy efficiency, device footprint and functional integration across sensing, computing and wireless applications.

Research from Nature Portfolio

Recent studies have realised sub-5 nm vertical-transport FETs that integrate a gate-controllable van der Waals heterojunction with a metal-filamentary threshold switch. These devices exhibit an average subthreshold swing below 60 mV/dec over six decades of drain current and an on/off ratio exceeding 10⁸, demonstrating exceptional area- and energy-efficiency for logic applications. Another innovative design dispenses with a semiconducting channel altogether, exploiting field emission across a graphene–hexagonal boron nitride interface to achieve an on/off ratio of 10⁶ and stable operation from 15 to 400 K. In this semiconductor-less vertical transistor, modulation of the emission barrier affords intrinsic gain up to four, resolving temperature-dependent performance issues and extending the operational envelope to extreme environments.

Research from all publishers

High-density vertical transistors have been realised by laminating a monolayer graphene–gold hybrid drain atop an ultrathin (3 nm) channel, achieving a record pitch size of 20 nm and on-state current densities above 700 A cm⁻². This approach enables three devices to be stacked within 59 nm of vertical distance, offering a new paradigm for footprint-constrained integration. In complementary work, nanoscale Schottky barrier characteristics at monolayer WSe₂/graphene junctions have been probed via Kelvin probe force microscopy and tip-enhanced photoluminescence under varying electrostatic doping. These measurements reveal near-ideal Schottky–Mott behaviour and quantifiable interface dipoles that dictate carrier injection, yielding actionable insights for contact engineering. Elsewhere, a graphene/MoSe₂ barristor employing a high-κ ion-gel gate dielectric has achieved ambipolar transport with an on/off ratio above 10⁴ and external quantum efficiency exceeding 60 per cent, illustrating the dual-function potential of heterostructure transistors as both switches and photodetectors.

Graphene-Based Field-Effect Transistors and Heterostructure Electronics publication trend

The graph below shows the total number of articles in graphene-based field-effect transistors and heterostructure electronics across all publications each year (not limited to Nature Index journals).

Technical terms

Graphene: A single atomic layer of carbon atoms arranged in a hexagonal lattice, noted for its high carrier mobility and mechanical strength.

Field-effect transistor (FET): A three-terminal device in which a gate voltage controls the conductivity of a semiconducting channel between source and drain.

Van der Waals heterostructure: An assembly of two-dimensional materials stacked by weak intermolecular forces, allowing atomically sharp interfaces without lattice matching.

Subthreshold swing: The gate-voltage change required to vary the drain current by one order of magnitude in the subthreshold region.

Schottky barrier: A potential‐energy barrier for charge carriers formed at a metal–semiconductor interface that governs injection and rectification.

References

1. Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures. Nature Communications (2024).
2. High‐Density Vertical Transistors with Pitch Size Down to 20 nm. Advanced Science (2023).
3. Semiconductor-less vertical transistor with ION/IOFF of 106. Nature Communications (2021).
4. Gate-tunable photodetector and ambipolar transistor implemented using a graphene/MoSe2 barristor. NPG Asia Materials (2021).
5. Probing Nanoscale Schottky Barrier Characteristics at WSe2/Graphene Heterostructures via Electrostatic Doping. Advanced Electronic Materials (2022).