Phase-Locked Loop Design in CMOS Technology

Phase-locked loops (PLLs) are indispensable timing and frequency synthesis circuits, finding application in communication transceivers, clock distribution, navigation receivers and sensor interfaces. Implemented in complementary metal-oxide-semiconductor (CMOS) technology, PLLs combine phase detectors, loop filters, voltage- or digitally-controlled oscillators and frequency dividers within a feedback architecture to achieve phase synchronisation. Advances in device scaling and mixed-signal integration have driven the emergence of fully digital and fractional-N synthesiser architectures, enabling fine resolution, low jitter and reduced power consumption. Key metrics include phase noise, integrated jitter, lock-time and power-area trade-offs, all of which are influenced by the choice of oscillator topology (ring, LC-tank or digitally-assisted), feedback path (analogue, subsampling or oversampling) and calibration strategies. Contemporary designs balance analogue performance with digital programmability, leveraging time-to-digital converters, ripple-suppression algorithms and duty-cycled frequency-locked loops to meet the stringent requirements of 5G, Internet-of-Things and millimetre-wave radar systems.

Research from Nature Portfolio

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Research from all publishers

Recent work has advanced ring-VCO-based PLLs for clock generation, presenting an analytical framework to benchmark power, jitter and area across architectures and to guide the selection of circuit techniques for diverse application scenarios. Another study has derived theoretical upper and lower limits for normalised loop bandwidth in digital PLLs for global navigation satellite system receivers, mapping stability criteria and measurement-error trade-offs as functions of loop-filter order, integration time and computational delay. Ultra-low-power fractional-N digital PLLs in 65-nm CMOS have demonstrated sub-300 μW operation by seamlessly switching between sampling and subsampling feedback paths, integrating a duty-cycled frequency-locked loop for robust acquisition and employing an efficient transformer-based gm-oscillator and truncated constant-slope digital-to-time converter to achieve jitter below 3 ps with excellent spur suppression.

Phase-Locked Loop Design in CMOS Technology publication trend

The graph below shows the total number of articles in phase-locked loop design in cmos technology across all publications each year (not limited to Nature Index journals).

Technical terms

Phase-locked loop (PLL): A feedback system that locks the phase of an output oscillator to that of a reference signal.

Voltage-controlled oscillator (VCO): An oscillator whose output frequency is tuned by an analogue control voltage.

Phase detector (PD): A circuit that compares the phase of two signals and generates an error voltage or digital code proportional to their phase difference.

Loop filter: A network that conditions the detector output to control the dynamics and stability of the PLL.

Fractional-N synthesis: A technique that achieves non-integer frequency division ratios by modulating the divider modulus over time.

Jitter: The temporal variation of zero-crossing instants in a periodic signal, often expressed as root-mean-square (rms) or peak-to-peak quantities.

References

1. Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art. Chip (2023).
2. Theoretical Upper and Lower Limits for Normalized Bandwidth of Digital Phase-Locked Loop in GNSS Receivers. Sensors (2023).
3. A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE Journal of Solid-State Circuits (2019).