Introduction

Indium-gallium-zinc oxide (IGZO) has emerged as a promising alternative to conventional amorphous silicon (a-Si) for thin-film transistor (TFT) applications, owing to its superior carrier mobility, compatibility with low-temperature processing, and low off-state current1,2,3. As a result, IGZO TFTs have been widely employed in commercial displays, particularly in active-matrix organic light-emitting diode (AMOLED) technologies4,5,6. Among the various IGZO TFT architectures, the self-aligned top-gate (SA TG) coplanar structure has been widely adopted for AMOLED backplanes, offering advantages such as low parasitic capacitance and enhanced process controllability7,8. As AMOLED displays push toward higher pixel densities, scaling the channel length of TFTs has become a key design requirement. However, it has been reported that in SA TG coplanar IGZO TFTs, both the electrical characteristics and long-term reliability can vary significantly with channel length9,10,11,12. In particular, several studies have shown that positive bias temperature stress (PBTS) reliability tends to improve as the channel length decreases13,14,15. This phenomenon has been discussed in previous studies with several hypotheses, but a clear physical explanation supported by experimental validation remains insufficient.

In this study, we investigated the origin of the channel-length-dependent PBTS behavior in SA TG coplanar IGZO TFTs. Devices with different channel lengths were characterized using high-low frequency capacitance-voltage (C-V) measurements and low-frequency noise (LFN) techniques. These methods allow for the quantitative extraction of the subgap density of states (DOS) in the IGZO channel and the near-interface trap density in the gate dielectric, both of which are key contributors to PBTS-induced degradation in IGZO TFTs. Our results indicate that the improved PBTS reliability in short-channel devices is associated with concurrent reductions in both the subgap DOS of the IGZO channel and the near-interface trap density in the gate dielectric. These findings provide physical insight into the channel-length-dependent degradation behavior in SA TG coplanar IGZO TFTs and offer guidance for the design of highly reliable IGZO TFTs for advanced display applications.

Result and discussion

Figure 1a presents a schematic cross-sectional view of the fabricated SA TG coplanar IGZO TFTs. The detailed fabrication procedure is provided in the Methods section. Figure 1b shows the transfer characteristics of devices with channel lengths (L) of 3 µm, 12 µm, and 20 µm, with a fixed channel width (W) of 10 µm, measured at room temperature (RT). During the measurements, the gate voltage (VG) was swept from − 15 V to + 15 V, while the drain voltage (VD) was held constant at 0.1 V, and the corresponding drain current (ID) was recorded. All electrical measurements were conducted using an Agilent 4156 C semiconductor parameter analyzer. Figure 1c summarizes the electrical parameters of SA TG coplanar IGZO TFTs with various Ls(W/L = 10 µm/3, 12, 20 µm). Each point is the mean of five devices for a given channel length, and the vertical error bars denote ± 1 standard deviation. The threshold voltage VTH was extracted as the gate voltage VG corresponding to ID = (W/L) × 1 nA. As the channel becomes shorter, VTH decreases, which is attributed to hydrogen diffusion from the n+-IGZO source/drain extension regions into the channel, increasing the carrier concentration16. The field-effect mobility µFE denotes the apparent mobility, extracted without considering the source/drain parasitic resistance Rext. It was computed in the linear region at VD = 0.1 V using µFE = gmL/WCOXVD, where gm is the transconductance and COX is the gate dielectric per unit area, and the reported value corresponds to the maximum extracted µFE. Consequently, shorter channels, for which the relative Rext is larger, exhibit a smaller extracted µFE despite their higher carrier concentration. The subthreshold swing SS was calculated as (dlog(ID)/dVG)−1 in the ID range of 10− 11 – 10− 10 A and decreases as L becomes shorter.

Figure 2a–c display the time evolution of the transfer characteristics for SA TG coplanar IGZO TFTs with channel lengths of (a) 3 µm, (b) 12 µm, and (c) 20 µm under PBTS conditions: overdrive voltage VOV (= VG - VTH) = 30 V, VS = VD = 0 V, and temperature = 60 ℃, where VS denotes the source voltage. Figure 2d summarizes the threshold voltage shift (ΔVTH) under PBTS for devices with different channel lengths as a function of stress time. From Fig. 2, it is observed that VTH increases with stress time in all devices: however, the ΔVTH values decrease as the channel length becomes shorter. This trend is consistent with previous reports indicating that short-channel SA TG coplanar IGZO TFTs exhibit improved PBTS stability compared to their long-channel counterparts13,14,15. Furthermore, the results in Fig. 2 clearly show that the device with a 3 µm channel length demonstrates particularly enhanced PBTS reliability relative to the devices with channel lengths of 12 µm and 20 µm.

To elucidate the physical mechanisms responsible for the phenomena observed in Fig. 2, we characterized the fabricated SA TG coplanar IGZO TFTs with various channel lengths using high-low frequency (f) C-V measurements and LFN techniques. Figure 3a–c present the normalized CG-VG (CG/COX-VG) curves measured at low (f = 100 Hz) and high (f = 1 MHz) frequencies for IGZO TFTs with L = (a) 3 µm, (b) 12 µm, (c) 20 µm, respectively. Here, CG denotes the gate-to-channel capacitance per unit area measured between the gate and the source/drain electrodes. C-V measurements were performed using a Solartron SI 1260 impedance analyzer coupled with an SI 1296 dielectric interface module. The results in Fig. 3a–c clearly demonstrate that the frequency-dependent dispersion of the normalized CG-VG characteristics becomes more pronounced with increasing channel length. In IGZO TFTs, the capacitance per unit area induced by localized subgap states (CLOC) can be extracted using the high-low frequency C-V method, as shown in Eq. (1)17,18, and the subgap DOS (g(E)) can be calculated using Eq. (2)19.

$${C_{LOC}}\,\,=\,\,\,\,\left[ {\,\,{{\left( {\frac{1}{{{C_{LF}}}}\,\, - \,\,\frac{1}{{{C_{OX}}}}} \right)}^{ - 1}}\,\, - \,\,{{\left( {\frac{1}{{{C_{HF}}}}\,\, - \,\,\frac{1}{{{C_{OX}}}}} \right)}^{ - 1}}\,\,} \right]\,\,\,\,\,[F/c{m^{ - 2}}]$$
(1)
$$g\,(E)\,\,=\,\,\frac{{{C_{LOC}}}}{{{q^2}{t_{IGZO}}}}\,\,\,\,\,[c{m^{ - 3}}e{V^{ - 1}}]$$
(2)

Here, CLF and CHF denote the gate-to-channel capacitance per unit area measured at low and high frequencies, respectively; tIGZO is the channel thickness of the TFTs; and q is the elementary charge. The surface potential (\(\:{\varphi\:}_{s}\)) can be nonlinearly mapped to VG using Eq. (3)20

$${\phi _s}({V_G})\;\;=\;\;\int\limits_{{{V_{FB}}}}^{{{V_G}}} {\;\;\left( {1 - \frac{{{C_G}({V_G})}}{{{C_{OX}}}}} \right)} \,\,\,d{V_G}\,\,\,[{\text{V}}]$$
(3)

where VFB is the flat-band voltage. Figure 3d presents the energy distribution of subgap DOS values extracted from the fabricated SA TG coplanar IGZO TFTs with L = 3 µm, 12 µm, and 20 µm near conduction band minimum (EC). The extracted subgap DOS values are divided into two components according to their energy level distribution: acceptor-like deep states (gDA) and acceptor-like tail states (gTA), in an increasing order of the energy levels. The subgap DOS profiles of each TFT near EC are well fitted with the following model

$$\begin{gathered} g\,(E)\,\, = \,\,g_{{DA}} \,(E)\,\, + \,\,g_{{TA}} \,(E)\,\, = \,\,N_{{DA}} \,\, \times \,\,\exp \,\,\left( {\frac{{E\,\, - \,\,E_{C} }}{{kT_{{DA}} }}} \right) \hfill \\ \,\,\,\,\, + \,\,N_{{TA}} \,\, \times \,\,\exp \left( {\frac{{E\,\, - \,\,E_{C} }}{{kT_{{TA}} }}} \right)\,\,\,\,[{\text{cm}}^{{ - 3}} {\text{eV}}^{{ - 1}} ] \hfill \\ \end{gathered}$$
(4)

where E is the electron energy; NDA and NTA are the densities of acceptor-like deep and tail states, extrapolated to EC, respectively; and kTDA and kTTA are the corresponding characteristic energies. Table 1 summarizes the subgap DOS parameters extracted from every TFT. Figure 3d and Table 1 indicate that the subgap DOS decreases with decreasing channel length in the fabricated SA TG IGZO TFTs. In particular, the subgap DOS extracted from the device with L = 3 µm is significantly lower than that extracted from the devices with L = 12 µm or 20 µm. Previous studies have reported that a high density of acceptor-like states can degrade the PBTS reliability of IGZO TFTs21,22,23,24. The experimental results in Fig. 3; Table 1 are consistent with those in Fig. 2 and suggest that the lower subgap DOS contributes to the superior PBTS reliability observed in the short-channel SA TG coplanar IGZO TFTs.

Table 1 Subgap DOS parameters extracted from the fabricated SA TG IGZO TFTs with different channel lengths (L = 3 µm, 12 µm, and 20 µm).
Full size table

Figure 4a–c show the frequency-dependent behavior of the normalized drain current noise power spectral density (SID/ID2), measured at various ID levels by sweeping VG under a fixed VD of 0.1 V, for SA TG coplanar IGZO TFTs with channel lengths of (a) 3 µm, (b) 12 µm, and (c) 20 µm, respectively. LFN characteristics were measured under ambient conditions at RT using an Agilent 89,441 vector signal analyzer and an SR570 low-noise current amplifier (Stanford Research Systems). Figure 5a–c present SID/ID2 as a function of ID at f = 10 Hz for each device. The symbols represent the experimental data, while the solid lines denote the fitting curves obtained using the modified LFN model described in Eq. (5), which was developed by our group to accurately capture the LFN behavior in SA TG coplanar oxide TFTs25.

$$\frac{{{S_{{I_D}}}}}{{{I_D}^{2}}}={\left( {1+{\alpha _C}{\mu _{eff}}{C_{OX}}\frac{{{I_D}}}{{{g_{mi}}}}} \right)^2}{\left( {\frac{{{R_{Ch}}}}{{{R_{Tot}}}}\frac{{{g_{mi}}}}{{{I_D}}}} \right)^2}\frac{{{q^2}kT\lambda {N_B}}}{{fW{L_{eff}}{C_{OX}}^{2}}}\,\,$$
(5)

This model extends the conventional ΔN-Δµ framework by incorporating structural effects unique to SA TG architectures-specifically, gate-length modulation (ΔL) and large source/drain parasitic resistance (Rext)-thereby enabling improved extraction of gate dielectric trap parameters in SA TG coplanar IGZO TFTs. Therefore, the quality of the gate dielectric can be evaluated more precisely and quantitatively, and it can be effectively used to analyze the reliability of devices, especially in short-channel structures where the influence of effective channel length and parasitic resistance elements are relatively large. In Eq. (5), NB is the near-interface trap density, k the Boltzmann constant, T the temperature, gmi the intrinsic transconductance, αC the Coulomb scattering coefficient, λ the tunneling attenuation length in the gate dielectric (= 10− 8 cm)26, and RCh and RTot the channel and total resistances, respectively. The effective mobility µeff is defined in Eq. (6), which accounts for the effective channel length (Leff = L - ΔL) and Rext extracted from the fabricated devices.

$${\mu _{eff}}=\frac{1}{{{C_{OX}}\left( {{V_D} - 2{I_D}{\operatorname{R} _{ext}}} \right)}}\frac{{{L_{eff}}}}{W}\frac{{\partial {I_D}}}{{\partial \left( {{V_G} - {I_D}{\operatorname{R} _{ext}}} \right)}}\,\,\,$$
(6)

Figure 5d and the inset present the extracted ΔL and W·Rext as functions of VG, obtained using the paired VG-based transmission line method at VD = 0.1 V27. Figure 6 illustrates the spatial profiles of NB as a function of tunneling depth from the IGZO/SiO2 interface, where the depth x is calculated from frequency via Eq. (7), assuming a characteristic interface time constant τ0 ≈ 10− 10s28.

$$x=\lambda \cdot \ln (\frac{1}{{2\pi f{\tau _0}}})\,\,$$
(7)

As shown in Fig. 6, the extracted NB values over the tunneling depth range (x ~ 1.1–1.4 nm) show a decreasing trend with shorter channel lengths, and this trend appears more noticeable in the device with L = 3 µm compared to those with L = 12 µm and 20 µm. Given that enhanced electron trapping into the gate dielectric under PBTS typically results in greater threshold voltage shifts29,30, this observation suggests that reduced NB near the IGZO/SiO2 interface also contributes to the improved PBTS reliability seen in the short-channel SA TG coplanar IGZO TFTs.

The experimental results presented in Figs. 3, 4, 5 and 6 clearly indicate that the enhanced PBTS reliability observed in shorter-channel SA TG coplanar IGZO TFTs is closely related to the simultaneous reduction in both the subgap DOS in the IGZO channel and the near-interface trap density in the SiO2 gate dielectric. To account for the observed behavior, we propose the following physical model to explain the underlying mechanism responsible for the improved PBTS reliability in short-channel devices, as illustrated in Fig. 7. In SA TG coplanar IGZO TFTs, the source/drain extension regions are heavily n+-doped, primarily due to the diffusion of hydrogen atoms originating from the PECVD-deposited ILD into the IGZO films. The role of hydrogen in IGZO TFTs has been reported to vary depending on its concentration31,32. Given that VTH and SS both decrease as the channel length decreases, this study focused on hydrogen serving dual roles as an electron donor (e.g., H0 → H+ + e-) and as a defect passivator (e.g., ≡M-O• + H → ≡M-OH)33,34,35. During the post-deposition annealing step, hydrogen diffuses from the n+-IGZO extension regions into the adjacent channel region, leading to an increased free electron concentration and suppressed subgap DOS in IGZO16. In addition, the elevated hydrogen concentration in the IGZO channel facilitates the subsequent diffusion of hydrogen into the SiO2 gate insulator. The incorporated hydrogen atoms can passivate pre-existing defects in SiO2, likely via hydrogen-related chemical reactions such as ≡ Si• + H → ≡Si-H36,37, thereby reducing the electrical trap density near the IGZO/SiO2 interface. Figure 7a and 7(b) schematically compare the spatial distributions of carrier concentration and hydrogen diffusion effects between short-channel (L = 3 µm) and long-channel (L = 12 or 20 µm) devices. Given that the effective hydrogen diffusion length from the n+-IGZO source/drain extension into the channel region is approximately 2.5-3.0 µm, as shown in Fig. 5d, it is plausible that almost the entire channel of the 3 µm device is subject to hydrogen-induced modifications. This may account for the markedly improved PBTS reliability of the shortest-channel device relative to its longer-channel counterparts. However, when the channel length becomes shorter than the hydrogen diffusion length (ΔL) from the n+-IGZO source/drain extension regions, the carrier concentration in the channel increases excessively, which may lead to abnormal device operation. Therefore, the excellent PBTS tendency for shorter channel devices should only be considered valid within the channel length range where normal operation is guaranteed. However, since ΔL in SA TG Coplanar Oxide TFTs varies depending on process conditions such as temperature during the post-deposition process, if normal operation characteristics are secured for devices with submicron-scale channel lengths through process optimization, the phenomenon observed in this study is expected to be valid for the relevant devices as well.

Conclusion

In this study, we conducted a comprehensive analysis to identify the physical mechanisms responsible for the channel-length-dependent PBTS reliability in SA TG coplanar IGZO TFTs. Our experimental results demonstrated that short-channel devices exhibited superior PBTS reliability, with a significantly reduced ΔVTH compared to longer-channel devices. To understand this phenomenon, we employed high-low frequency C-V and LFN characterization methods. The C-V analysis revealed a clear trend: the subgap DOS in the IGZO channel decreased as the channel length was reduced. Concurrently, LFN measurements showed that the near-interface trap density in the SiO2 gate dielectric also decreased with shorter channel lengths. These findings confirm that both the IGZO bulk properties and the quality of the SiO2 gate dielectric are improved in shorter-channel devices. We possibly attribute this improvement to hydrogen diffusion from the n+-IGZO source/drain extensions during fabrication, which may passivate defects in both regions. In particular, in devices with L = 3 µm, almost the entire channel lies within the effective hydrogen diffusion range, leading to a substantial reduction in defect density and, consequently, improved PBTS reliability.

Methods

The fabrication process commenced with the deposition of a 300 nm-thick SiO2 buffer layer on a glass substrate via plasma-enhanced chemical vapor deposition (PECVD). A 30 nm-thick amorphous IGZO film (In: Ga: Zn = 1:1:1 mol%) was subsequently formed at room temperature using DC magnetron sputtering. A 150 nm-thick SiO2 gate dielectric was then deposited through PECVD, followed by the formation of a Cu/MoTi gate electrode using DC sputtering. After photolithographic definition of both the gate and gate insulator layers, interlayer dielectric (ILD) films consisting of SiOx and SiNx were sequentially deposited by PECVD and patterned to create contact vias. Source and drain electrodes composed of Cu/MoTi were then deposited and patterned to align with the gate, completing the formation of n+-IGZO source/drain extension regions. During this process, hydrogen atoms originating from the PECVD-deposited ILD layers diffused into the IGZO films, donating electrons and thereby modulating its conductivity in the source/drain extension regions. Finally, a top passivation layer of SiO2 was deposited over the entire device structure, and thermal annealing was performed to stabilize electrical characteristics and improve film uniformity.

Fig. 1
figure 1

(a) Schematic cross-sectional of the fabricated SA TG coplanar IGZO TFTs. (b) Transfer characteristics of the SA TG coplanar IGZO TFTs with various Ls (W/L = 10 µm/3, 12, 20 µm) measured in the linear region (VD = 0.1 V) at RT. (c) VTH, µFE, and SS values extracted from the SA TG coplanar IGZO TFTs with various Ls (W/L = 10 µm/3, 12, 20 µm), where each value represents the average of five devices, and the vertical error bars indicate ± 1 standard deviation.

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Fig. 2
figure 2

Time evoluition of the transfer characteristics for SA TG coplanar IGZO TFTs with channel lengths of (a) 3 µm, (b) 12 µm, and (c) 20 µm under PBTS of VOV = 30 V and VS = VD = 0 V at 60 ℃. (d) ΔVTH values under PBTS for IGZO TFTs with different channel lengths as a function of stress time.

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Fig. 3
figure 3

Normalized CG-VG (CG/COX-VG) curves measured at low (f = 100 Hz) and high (f = 1 MHz) frequencies for SA TG coplanar IGZO TFTs with channel lengths of (a) 3 µm, (b) 12 µm and (c) 20 µm. (d) Energy distribution of subgap DOS value (g(E)) extracted from the fabricated SA TG coplanar IGZO TFTs with L = 3 µm, 12 µm, and 20 µm near EC.

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Fig. 4
figure 4

Frequency dependence of SID/ID2 values measured at various IDs for SA TG coplanar IGZO TFTs with channel lengths of (a) 3 µm, (b) 12 µm, and (c) 20 µm.

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Fig. 5
figure 5

SID/ID2 versus ID plot for SA TG coplanar IGZO TFTs with channel lengths of (a) 3 µm, (b) 12 µm, and (c) 20 µm. The symbols represent the experimental data, while the solid lines denote the fitting curves obtained using the modified LFN model. (d) ΔL values as a function of VG; the inset shows W·Rext versus VG, both extracted using the VG-based transmission line method.

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Fig. 6
figure 6

Spatial distribution of NBs with respect to the distance from the IGZO/SiO2 interface in SA TG coplanar IGZO TFTs with channel lengths of (a) 3 µm, (b) 12 µm, and (c) 20 µm.

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Fig. 7
figure 7

Comparison of the spatial distributions of carrier concentration and hydrogen diffusion effects in (a) short-channel (L = 3 µm) and (b) long-channel (L = 12 or 20 µm) SA TG coplanar IGZO TFTs.

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