The simultaneous scaling down of the channel length and gate length of 2D transistors remains challenging. Here, the authors report a self-alignment process to fabricate vertical MoS2 transistors with sub-1 nm gate length and sub−50 nm channel length, exhibiting on-off ratios over 105 and on-state currents of 250 μA/μm at 4 V bias.
- Liting Liu
- Yang Chen
- Yuan Liu